ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
Address 0x6D
EEPROM Register 13 | |||||||
---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_SEL[1:0] | SEL_DIVIDER | EN_PLL | SYNC_PRE_DIVIDER[3:0] |
Name | Bit | Access | Description |
---|---|---|---|
R_SEL[1:0] | 7:6 | R/W | Coefficient for the slow PLL divider
00 = 16 01 = 32 10 = 64 11 = 128 |
SEL_DIVIDER | 5 | R/W | PLL divider selection
0 = Slow PLL divider with external compensation (when using VSYNC) 1 = Fast PLL divider with internal compensation (when using 5-MHz internal clock) |
EN_PLL | 4 | R/W | PLL enable
0 = PLL disabled and internal 5-MHz oscillator used for PWM generation 1 = PLL is used for generating the PWM generation clock from the internal oscillator or VSYNC signal |
SYNC_PRE_DIVIDER[3:0] | 3:0 | R/W | VSYNC signal pre-divider from 1 to 16. Used when VSYNC frequency is higher than PWM output frequency. |