ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
Address 0x6C
EEPROM Register 12 | |||||||
---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_SYNC | PWM_SYNC | PWM_COUNTER_RESET | SLOW_PLL_DIV[4:0] |
Name | Bit | Access | Description |
---|---|---|---|
EN_SYNC | 7 | R/W | VSYNC input enable
0 = VSYNC input disabled 1 = VSYNC input enabled |
PWM_SYNC | 6 | R/W | Enable PWM generation synchronization to VSYNC signal
0 = Disabled 1 = Enabled. PWM output used for phase detector input after dividing with SLOW_PLL_DIV divider |
PWM_COUNTER_RESET | 5 | R/W | Enable PWM generator resetting on VSYNC signal rising edge
0 = Disabled 1 = Enabled |
SLOW_PLL_DIV[4:0] | 4:0 | R/W | Divider for VSYNC operation. 5 LSB bits |