4 修订历史
Changes from F Revision (May 2013) to G Revision
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Added 引脚配置和功能部分,ESD 额定值表,特性描述部分,器件功能模式,应用和实施部分,电源相关建议部分,布局部分,器件和文档支持部分以及机械、封装和可订购信息部分Go
Changes from E Revision (February 2013) to F Revision
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Added 器件名称至文档标题。Go
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Changed 所有 LLP 和 QFN 封装至 WQFN 封装(通篇)。Go
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Deleted optional from CLKin* pin description. And changed complimentary to complementary.Go
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Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table.Go
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Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table.Go
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Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table.Go
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Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table.Go
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Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table.Go
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Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. Go
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Deleted VIL table note.Go
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Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
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Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under CLKin column.Go
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Changed table title from CLKin input vs. Output States to OSCin Input vs. Output StatesGo
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Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra references to other figures. Revised to better correspond with information in Electrical Characteristics Table.Go
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Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs sectionGo
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Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
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Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
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Deleted sentence in reference to two deleted images.Go
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Changed link from National packaging site to TI packaging site.Go