ZHCSDM5G March   2012  – December 2014 LMK00105

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史
  5. 5 Pin Configuration and Diagrams
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Vdd and Vddo Power Supplies
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Selection of Clock Input
          1. 7.3.2.1.1 CLKin/CLKin* Pins
          2. 7.3.2.1.2 OSCin/OSCout Pins
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Output Enable Pin
        2. 7.3.3.2 Using Less than Five Outputs
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Inputs
      2. 8.1.2 Clock Outputs
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Block Diagram
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Crystal Interface
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Filtering
    2. 9.2 Power Supply Ripple Rejection
    3. 9.3 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground Planes
      2. 10.1.2 Power Supply Pins
      3. 10.1.3 Differential Input Termination
      4. 10.1.4 Output Termination
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 差分电压测量术语
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Power Supply Recommendations

9.1 Power Supply Filtering

It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply to isolate the high-frequency switching noises generated by the clock driver, preventing them from leaking into the board supply. Choosing an appropriate ferrite bead with very low DC resistance is important, because it is imperative to provide adequate isolation between the board supply and the chip supply. It is also imperative to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation.

LMK00105 powersupp_snas579.pngFigure 21. Power-Supply Decoupling

9.2 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vddo supply. The PSRR test setup is shown in Figure 22.

LMK00105 30180740.gifFigure 22. PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto the Vddo supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions:

  • Ripple amplitude: 100 mVpp on Vddo = 2.5 V
  • Ripple frequency: 100 kHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

Equation 5. DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / (π * fclk)] * 1012

9.3 Power Supply Bypassing

The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance.