ZHCSEN7D October   2014  – February 2022 DS90UB948-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
        1. 7.4.2.1 Dual Swap
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
        1. 7.5.3.1 LUT Programming Example
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Controller Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Controller Operation
      4. 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.7.1 DS90UB948-Q1 Registers

Table 7-12 lists the memory-mapped registers for the DS90UB948-Q1 registers. All register offset addresses not listed in Table 7-12 should be considered as reserved locations and the register contents should not be modified.

Table 7-12 DS90UB948-Q1 Registers
AddressAcronymRegister NameSection
0x0I2C_DEVICE_IDGo
0x1RESETGo
0x2GENERAL_CONFIGURATION_0Go
0x3GENERAL_CONFIGURATION_1Go
0x4BCC_WATCHDOG_CONTROLGo
0x5I2C_CONTROL_1Go
0x6I2C_CONTROL_2Go
0x7REMOTE_IDGo
0x8TargetID_0Go
0x9TargetID_1Go
0xATargetID_2Go
0xBTargetID_3Go
0xCTargetID_4Go
0xDTargetID_5Go
0xETargetID_6Go
0xFTargetID_7Go
0x10TargetALIAS_0Go
0x11TargetALIAS_1Go
0x12TargetALIAS_2Go
0x13TargetALIAS_3Go
0x14TargetALIAS_4Go
0x15TargetALIAS_5Go
0x16TargetALIAS_6Go
0x17TargetALIAS_7Go
0x18MAILBOX_18Go
0x19MAILBOX_19Go
0x1AGPIO_9__and_GLOBAL_GPIO_CONFIGGo
0x1BFREQUENCY_COUNTERGo
0x1CGENERAL_STATUSGo
0x1DGPIO0_CONFIGGo
0x1EGPIO1_2_CONFIGGo
0x1FGPIO3_CONFIGGo
0x20GPIO5_6_CONFIGGo
0x21GPIO7_8_CONFIGGo
0x22DATAPATH_CONTROLGo
0x23RX_MODE_STATUSGo
0x24BIST_CONTROLGo
0x25BIST_ERROR_COUNTGo
0x26SCL_HIGH_TIMEGo
0x27SCL_LOW_TIMEGo
0x28DATAPATH_CONTROL_2Go
0x29FRC_CONTROLGo
0x2AWHITE_BALANCE_CONTROLGo
0x2BI2S_CONTROLGo
0x2EPCLK_TEST_MODEGo
0x34DUAL_RX_CTLGo
0x35AEQ_TESTGo
0x37MODE_SELGo
0x3AI2S_DIVSELGo
0x3BEQ_STATUSGo
0x41LINK_ERROR_COUNTGo
0x43HSCC_CONTROLGo
0x44ADAPTIVE_EQ_BYPASSGo
0x45ADAPTIVE_EQ_MIN_MAXGo
0x49FPD_TX_MODEGo
0x4BLVDS_CONTROLGo
0x52CML_OUTPUT_CTL1Go
0x56CML_OUTPUT_ENABLEGo
0x57CML_OUTPUT_CTL2Go
0x63CML_OUTPUT_CTL3Go
0x64PGCTLGo
0x65PGCFGGo
0x66PGIAGo
0x67PGIDGo
0x68PGDBGGo
0x69PGTSTDATGo
0x6EGPI_PIN_STATUS_1Go
0x6FGPI_PIN_STATUS_2Go
0xF0RX_ID0Go
0xF1RX_ID1Go
0xF2RX_ID2Go
0xF3RX_ID3Go
0xF4RX_ID4Go
0xF5RX_ID5Go

7.7.1.1 I2C_DEVICE_ID Register (Address = 0x0) [reset = STRAP]

I2C_DEVICE_ID is shown in and described in Table 7-13.

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Table 7-13 I2C_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7-1DEVICE_IDR/WSTRAP7-bit address of Deserializer
Defaults to address configured by the IDX strap pin
0DES_IDR/W0x00: Device ID is from IDX strap
1: Register I2C Device ID overrides IDX strap

7.7.1.2 RESET Register (Address = 0x1) [reset = 0x0]

RESET is described in Table 7-14.

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Table 7-14 RESET Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6RESERVEDR0x0Reserved
5RESERVEDR0x0Reserved
4RESERVEDR0x0Reserved
3RESERVEDR0x0Reserved
2BC_ENABLER/W0x1Back Channel enable.
Note: This bit can not be set to 0 through the control channel, it is only writable via local I2C at the DES.
Note: Setting this bit to 0 will disable the back channel only if both I2C pass through bits, 0x03[3] and 0x05[7], are also set to low.
1DIGITAL_RESET0R/W0x0Digital Reset
Resets the entire digital block including registers. This bit is self-clearing.
1: Reset
0: Normal operation
Registers which are loaded by pin strap will be restored to their original strap value when this bit is set. These registers show 'Strap ' as their default value in this table.
0DIGITAL_RESET1R/W0x0Digital Reset
Resets the entire digital block except registers. This bit is self-clearing.
1: Reset
0: Normal operation
Note: After a digital reset, the following registers are not reset:

0x00, 0x01[4:3, 1:0], 0x23[4:3], 0x2A[7:6], 0x32[0], 0x34[4:0], 0x49[1:0], 0x71[5]

7.7.1.3 GENERAL_CONFIGURATION_0 Register (Address = 0x2) [reset = 0x0]

GENERAL_CONFIGURATION_0 is described in Table 7-15.

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Table 7-15 GENERAL_CONFIGURATION_0 Register Field Descriptions
BitFieldTypeResetDescription
7OUTPUT_ENABLER/W0x0Output Enable Override Value (in conjunction with Output Sleep State Select)
If the Override control is not set, the Output Enable will be set to 1.
A Digital reset 0x01[0] should be asserted after toggling Output Enable bit LOW to HIGH
6OUTPUT_ENABLE_OVERRIDER/W0x0Overrides Output Enable and Output Sleep State default
0: Disable override
1: Enable override
5OSC_CLOCK_OUTPUT_ENABLE__AUTO_CLOCK_ENR/W0x0OSC clock output enable
If loss of lock OSC clock is output onto PCLK. The frequency is selected in register 0x24.
1: Enable
0: Disable
4OUTPUT_SLEEP_STATE_SELECTR/W0x0OSS Select Override value to control output state when LOCK is low (used in conjunction with Output Enable)
If the Override control is not set, the Output Sleep State Select will be set to 1.
3RESERVEDR0x0Reserved
2RESERVEDR0x0Reserved
1RESERVEDR0x0Reserved
0RESERVEDR0x0Reserved

7.7.1.4 GENERAL_CONFIGURATION_1 Register (Address = 0x3) [reset = 0xF0]

GENERAL_CONFIGURATION_1 is described in Table 7-16.

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Table 7-16 GENERAL_CONFIGURATION_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x1Reserved
6BC_CRC_GENERATOR_ENABLER/W0x1Back Channel CRC Generator Enable
0: Disable
1: Enable
5FAILSAFE_LOWR/W0x1Controls the pull direction for undriven LVCMOS inputs
1: Pull down
0: Pull up
4FILTER_ENABLER/W0x1HS,VS,DE two clock filter
When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected. For HS, It is a 2-clock filter for single FPD3 mode and a 4-clock filter for dual FPD3 mode.
1: Filtering enable
0: Filtering disable
3I2C_PASS_THROUGHR/W0x0I2C Pass-Through to Serializer if decode matches
0: Pass-Through Disabled
1: Pass-Through Enabled
2AUTO_ACKR/W0x0Automatically Acknowledge I2C writes independent of the forward channel lock state
1: Enable
0: Disable
1DE_GATE_RGBR/W0x0Gate RGB data with DE signal. RGB data is gated with DE in order to allow packetized audio and block unencrypted data when paired with a serializer that supports HDCP. When paired with a serializer that does not support HDCP, RGB data is not gated with DE by default. However, to enable packetized autio this bit must be set.
1: Gate RGB data with DE (has no effect when paired with a serializer that supports HDCP)
0: Pass RGB data independent of DE (has no effect when paired with a serializer that does not support HDCP)
0RESERVEDR0x0Reserved

7.7.1.5 BCC_WATCHDOG_CONTROL Register (Address = 0x4) [reset = 0xFE]

BCC_WATCHDOG_CONTROL is described in Table 7-17.

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Table 7-17 BCC_WATCHDOG_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-1BCC_WATCHDOG_TIMERR/W0x7FThe watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0.
0BCC_WATCHDOG_TIMER_DISABLER/W0x0Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation

7.7.1.6 I2C_CONTROL_1 Register (Address = 0x5) [reset = 0x1E]

I2C_CONTROL_1 is described in Table 7-18.

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Table 7-18 I2C_CONTROL_1 Register Field Descriptions
BitFieldTypeResetDescription
7I2C_PASS_THROUGH_ALLR/W0x0I2C Pass-Through All Transactions
0: Disabled
1: Enabled
6-4I2C_SDA_HOLDR/W0x1Internal SDA Hold Time
This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds.
3-0I2C_FILTER_DEPTHR/W0xEI2C Glitch Filter Depth
This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds.

7.7.1.7 I2C_CONTROL_2 Register (Address = 0x6) [reset = 0x0]

I2C_CONTROL_2 is described in Table 7-19.

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Table 7-19 I2C_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
7FORWARD_CHANNEL_SEQUENCE_ERRORR0x0Control Channel Sequence Error Detected
This bit indicates a sequence error has been detected in forward control channel. If this bit is set, an error may have occurred in the control channel operation.
6CLEAR_SEQUENCE_ERRORR/W0x0Clears the Sequence Error Detect bit
5RESERVEDR0x0Reserved
4-3SDA_Output_DelayR/W0x0SDA Output Delay
This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50ns. Nominal output delay values for SCL to SDA are:
00: 250ns
01: 300ns
10: 350ns
11: 400ns
2LOCAL_WRITE_DISABLER/W0x0Disable Remote Writes to Local Registers
Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C Controller attached to the Serializer. Setting this bit does not affect remote access to I2C Targets at the Deserializer.
1I2C_BUS_TIMER_SPEEDUPR/W0x0Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50 microseconds
0: Watchdog Timer expires after approximately 1 second.
0I2C_BUS_TIMER_DISABLER/W0x0Disable I2C Bus Watchdog Timer
When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL

7.7.1.8 REMOTE_ID Register (Address = 0x7) [reset = 0x0]

REMOTE_ID is described in Table 7-20.

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Table 7-20 REMOTE_ID Register Field Descriptions
BitFieldTypeResetDescription
7-1REMOTE_IDR/W0x07-bit Serializer Device ID
Configures the I2C Target ID of the remote Serializer. A value of 0 in this field disables I2C access to the remote Serializer. This field is automatically loaded from the Serializer once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent loading by the Bidirectional Control Channel.
0FREEZE_DEVICE_IDR/W0x0Freeze Serializer Device ID
Prevent auto-loading of the Serializer Device ID from the Forward Channel. The ID will be frozen at the value written.

7.7.1.9 TargetID_0 Register (Address = 0x8) [reset = 0x0]

TargetID_0 is described in Table 7-21.

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Table 7-21 TargetID_0 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID0R/W0x07-bit Remote Target Device ID 0
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.10 TargetID_1 Register (Address = 0x9) [reset = 0x0]

TargetID_1 is described in Table 7-22.

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Table 7-22 TargetID_1 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID1R/W0x07-bit Remote Target Device ID 1
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.11 TargetID_2 Register (Address = 0xA) [reset = 0x0]

TargetID_2 is described in Table 7-23.

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Table 7-23 TargetID_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID2R/W0x07-bit Remote Target Device ID 2
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.12 TargetID_3 Register (Address = 0xB) [reset = 0x0]

TargetID_3 is described in Table 7-24.

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Table 7-24 TargetID_3 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID3R/W0x07-bit Remote Target Device ID 3
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.13 TargetID_4 Register (Address = 0xC) [reset = 0x0]

TargetID_4 is described in Table 7-25.

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Table 7-25 TargetID_4 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID4R/W0x07-bit Remote Target Device ID 4v Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.14 TargetID_5 Register (Address = 0xD) [reset = 0x0]

TargetID_5 is described in Table 7-26.

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Table 7-26 TargetID_5 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID5R/W0x07-bit Remote Target Device ID 5
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.15 TargetID_6 Register (Address = 0xE) [reset = 0x0]

TargetID_6 is described in Table 7-27.

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Table 7-27 TargetID_6 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID6R/W0x07-bit Remote Target Device ID 6
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.16 TargetID_7 Register (Address = 0xF) [reset = 0x0]

TargetID_7 is described in Table 7-28.

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Table 7-28 TargetID_7 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ID7R/W0x07-bit Remote Target Device ID 7
Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0RESERVEDR0x0Reserved

7.7.1.17 TargetALIAS_0 Register (Address = 0x10) [reset = 0x0]

TargetALIAS_0 is described in Table 7-29.

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Table 7-29 TargetALIAS_0 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID0R/W0x07-bit Remote Target Device Alias ID 0
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID0 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.18 TargetALIAS_1 Register (Address = 0x11) [reset = 0x0]

TargetALIAS_1 is described in Table 7-30.

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Table 7-30 TargetALIAS_1 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID1R/W0x07-bit Remote Target Device Alias ID 1
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID1 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.19 TargetALIAS_2 Register (Address = 0x12) [reset = 0x0]

TargetALIAS_2 is described in Table 7-31.

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Table 7-31 TargetALIAS_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID2R/W0x07-bit Remote Target Device Alias ID 2
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID2 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.20 TargetALIAS_3 Register (Address = 0x13) [reset = 0x0]

TargetALIAS_3 is described in Table 7-32.

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Table 7-32 TargetALIAS_3 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID3R/W0x07-bit Remote Target Device Alias ID 3
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID3 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.21 TargetALIAS_4 Register (Address = 0x14) [reset = 0x0]

TargetALIAS_4 is described in Table 7-33.

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Table 7-33 TargetALIAS_4 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID4R/W0x07-bit Remote Target Device Alias ID 4
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID4 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.22 TargetALIAS_5 Register (Address = 0x15) [reset = 0x0]

TargetALIAS_5 is described in Table 7-34.

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Table 7-34 TargetALIAS_5 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID5R/W0x07-bit Remote Target Device Alias ID 5
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID5 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.23 TargetALIAS_6 Register (Address = 0x16) [reset = 0x0]

TargetALIAS_6 is described in Table 7-35.

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Table 7-35 TargetALIAS_6 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID6R/W0x07-bit Remote Target Device Alias ID 6
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID6 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.24 TargetALIAS_7 Register (Address = 0x17) [reset = 0x0]

TargetALIAS_7 is described in Table 7-36.

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Table 7-36 TargetALIAS_7 Register Field Descriptions
BitFieldTypeResetDescription
7-1Target_ALIAS_ID7R/W0x07-bit Remote Target Device Alias ID 7
Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction will be remapped to the address specified in the Target ID7 register. A value of 0 in this field disables access to the remote I2C Target.
0RESERVEDR0x0Reserved

7.7.1.25 MAILBOX_18 Register (Address = 0x18) [reset = 0x0]

MAILBOX_18 is described in Table 7-37.

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Table 7-37 MAILBOX_18 Register Field Descriptions
BitFieldTypeResetDescription
7-0MAILBOX_18R/W0x0Mailbox Register
This register is an unused read/write register that can be used for any purpose such as passing messages between I2C Controllers on opposite ends of the link.

7.7.1.26 MAILBOX_19 Register (Address = 0x19) [reset = 0x1]

MAILBOX_19 is described in Table 7-38.

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Table 7-38 MAILBOX_19 Register Field Descriptions
BitFieldTypeResetDescription
7-0MAILBOX_19R/W0x1Mailbox Register
This register is an unused read/write register that can be used for any purpose such as passing messages between I2C Controllers on opposite ends of the link.

7.7.1.27 GPIO_9__and_GLOBAL_GPIO_CONFIG Register (Address = 0x1A) [reset = 0x0]

GPIO_9__and_GLOBAL_GPIO_CONFIG is described in Table 7-39.

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Table 7-39 GPIO_9__and_GLOBAL_GPIO_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7GLOBAL_GPIO_OUTPUT_VALUER/W0x0Global GPIO Output Value
This value is output on each GPIO pin when the individual pin is not otherwise enabled as a GPIO and the global GPIO direction is Output
6RESERVEDR0x0Reserved
5GLOBAL_GPIO_FORCE_DIRR/W0x0The GLOBAL GPIO DIR and GLOBAL GPIO EN bits configure the pad in input direction or output direction for functional mode or GPIO mode. The GLOBAL bits are overridden by the individual GPIO DIR and GPIO EN bits.
{GLOBAL GPIO DIR, GLOBAL GPIO EN}
00: Functional mode; output
10: Tri-state
01: Force mode; output
11: Force mode; input
4GLOBAL_GPIO_FORCE_ENR/W0x0This bit grouped together with bit 5 to form the configuration of GPIO DIR and GPIO EN.
3GPIO9_OUTPUT_VALUER/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2RESERVEDR0x0Reserved
1GPIO9_DIRR/W0x0The GPIO DIR and GPIO EN bits configure the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
0GPIO9_ENR/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.

7.7.1.28 FREQUENCY_COUNTER Register (Address = 0x1B) [reset = 0x0]

FREQUENCY_COUNTER is shown in and described in Table 7-40.

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Table 7-40 FREQUENCY_COUNTER Register Field Descriptions
BitFieldTypeResetDescription
7-0Frequency_CountR/W0x0Frequency Counter control
A write to this register will enable a frequency counter to count the number of pixel clock during a specified time interval. The time interval is equal to the value written multiplied by the oscillator clock period (nominally 50ns). A read of the register returns the number of pixel clock edges seen during the enabled interval. The frequency counter will freeze at 0xff if it reaches the maximum value. The frequency counter will provide a rough estimate of the pixel clock period. If the pixel clock frequency is known, the frequency counter may be used to determine the actual oscillator clock frequency.

7.7.1.29 GENERAL_STATUS Register (Address = 0x1C) [reset = 0x0]

GENERAL_STATUS is described in Table 7-41.

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Table 7-41 GENERAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0Reserved
5DUAL_TX_STSR0x0Transmitter Dual Link Status:
This bit indicates the current operating mode of the FPD-Link Transmit port
1: Dual-link mode active
0: Single-link mode active
4DUAL_RX_STSR0x0Receiver Dual Link Status:
This bit indicates the current operating mode of the FPD-Link III Receive port
1: Dual-link mode active
0: Single-link mode active
3I2S_LOCKEDR0x0I2S LOCK STATUS
0: I2S PLL controller not locked
1: I2S PLL controller locked to input i2s clock
2RESERVEDR0x0Reserved
1SIGNAL_DETECTR0x01: Serial input detected
0: Serial input not detected
0LOCKR0x0De-Serializer CDR, PLL's clock to recovered clock frequency
1: De-Serializer locked to recovered clock
0: De-Serializer not locked
In Dual-link mode, this indicates both channels are locked.

7.7.1.30 GPIO0_CONFIG Register (Address = 0x1D) [reset = 0x10]

GPIO0_CONFIG is described in Table 7-42.

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GPIO0 and D_GPIO0 Configuration: If PORT1_SEL is set, this register controls the D_GPIO0 pin

Table 7-42 GPIO0_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-4Rev_IDR0x1Revision ID
0001: B1
3GPIO0_OUTPUT_VALUE
_D_GPIO0_OUTPUT_VALUE		R/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2GPIO0_REMOTE_ENABLE
_D_GPIO0_REMOTE_ENABLE		R/W0x0Remote GPIO Control
1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Serializer.
0: Disable GPIO control from remote Serializer.
1GPIO0_DIR
_D_GPIO0_DIR		R/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
*Reset value is 1 when PORT1_SEL = 1
0GPIO0_EN
_D_GPIO0_EN		R/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.
*Reset value is 1 when PORT1_SEL = 1

7.7.1.31 GPIO1_2_CONFIG Register (Address = 0x1E) [reset = 0x00]

GPIO1_2_CONFIG is described in Table 7-43.

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GPIO1/GPIO2 and D_GPIO1/D_GPIO2 Configuration: If PORT1_SEL is set, this register controls the D_GPIO1 and D_GPIO2 pins

Table 7-43 GPIO1_2_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7GPIO2_OUTPUT_VALUE
_D_GPIO2_OUTPUT_VALUE		R/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
6GPIO2_REMOTE_ENABLE
_D_GPIO2_REMOTE_ENABLE		R/W0x0Remote GPIO Control
1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Serializer.
0: Disable GPIO control from remote Serializer.
5GPIO2_DIR
_D_GPIO2_DIR		R/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
*Reset value is 1 when PORT1_SEL = 1
4GPIO2_EN
_D_GPIO2_EN		R/W0x0This bit grouped together with bit 5 to form the configuration of GPIO DIR and GPIO EN.
*Reset value is 1 when PORT1_SEL = 1
3GPIO1_OUTPUT_VALUE
_D_GPIO1_OUTPUT_VALUE		R/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2GPIO1_REMOTE_ENABLE
_D_GPIO1_REMOTE_ENABLE		R/W0x0Remote GPIO Control
1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Serializer.
0: Disable GPIO control from remote Serializer.
1GPIO1_DIR
_D_GPIO1_DIR		R/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
*Reset value is 1 when PORT1_SEL = 1
0GPIO1_EN
_D_GPIO1_EN		R/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.
*Reset value is 1 when PORT1_SEL = 1

7.7.1.32 GPIO3_CONFIG Register (Address = 0x1F) [reset = 0x00]

GPIO3_CONFIG is described in Table 7-44.

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GPIO3 and D_GPIO3 Configuration: If PORT1_SEL is set, this register controls the D_GPIO3 pin

Table 7-44 GPIO3_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0Reserved
3GPIO3_OUTPUT_VALUE
_D_GPIO3_OUTPUT_VALUE		R/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2GPIO3_REMOTE_ENABLE
_D_GPIO3_REMOTE_ENABLE		R/W0x0Remote GPIO Control
1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Serializer.
0: Disable GPIO control from remote Serializer.
1GPIO3_DIR
_D_GPIO3_DIR		R/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
*Reset value is 1 when PORT1_SEL = 1
0GPIO3_EN
_D_GPIO3_EN		R/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.
*Reset value is 1 when PORT1_SEL = 1

7.7.1.33 GPIO5_6_CONFIG Register (Address = 0x20) [reset = 0x0]

GPIO5_6_CONFIG is described in Table 7-45.

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Table 7-45 GPIO5_6_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7GPIO6_OUTPUT_VALUER/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
6ReservedR/W0x0Reserved
5GPIO6_DIRR/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
4GPIO6_ENR/W0x0This bit grouped together with bit 5 to form the configuration of GPIO DIR and GPIO EN.
3GPIO5_OUTPUT_VALUER/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2ReservedR/W0x0Reserved
1GPIO5_DIRR/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
0GPIO5_ENR/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.

7.7.1.34 GPIO7_8_CONFIG Register (Address = 0x21) [reset = 0x0]

GPIO7_8_CONFIG is described in Table 7-46.

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Table 7-46 GPIO7_8_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7GPIO8_OUTPUT_VALUER/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
6ReservedR/W0x0Reserved
5GPIO8_DIRR/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
4GPIO8_ENR/W0x0This bit grouped together with bit 5 to form the configuration of GPIO DIR and GPIO EN.
3GPIO7_OUTPUT_VALUER/W0x0Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2ReservedR/W0x0Reserved
1GPIO7_DIRR/W0x0The GPIO DIR and GPIO EN configures the pad in input direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
0GPIO7_ENR/W0x0This bit grouped together with bit 1 to form the configuration of GPIO DIR and GPIO EN.

7.7.1.35 DATAPATH_CONTROL Register (Address = 0x22) [reset = 0x0]

DATAPATH_CONTROL is described in Table 7-47.

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Table 7-47 DATAPATH_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7OVERRIDE_FC_CONFIGR/W0x01: Disable loading of this register from the forward channel, keeping locally written values intact 0: Allow forward channel loading of this register
6PASS_RGBR/W0x0Setting this bit causes RGB data to be sent independent of DE. This allows operation in systems which may not use DE to frame video data or send other data when DE is deasserted. Note that setting this bit prevents HDCP operation and blocks packetized audio. This bit does not need to be set in DS90UB928 or in Backward Compatibility mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.
5DE_POLARITYR/W0x0This bit indicates the polarity of the DE (Data Enable) signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.
4I2S_RPTR_REGENR/W0x0This bit controls whether the HDCP Receiver outputs packetized Auxiliary/Audio data on the RGB video output pins.
1: Don't output packetized audio data on RGB video output pins
0: Output packetized audio on RGB video output pins.
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.
3I2S_4_CHANNEL_ENABLE_OVERRIDER/W0x01: Set I2S 4-Channel Enable from bit of of this register
0: Set I2S 4-Channel disabled
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.
218_BIT_VIDEO_SELECTR/W0x01: Select 18-bit video mode
0: Select 24-bit video mode
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.Note: Surround audio is not supported in repeater mode when 18-bit video mode is enabled.
1I2S_TRANSPORT_SELECTR/W0x01: Enable I2S In-Band Transport
0: Enable I2S Data Island Transport
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.
0I2S_4_CHANNEL_ENABLER/W0x0I2S 4-Channel Enable
1: Enable I2S 4-Channel
0: Disable I2S 4-Channel
Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set.

7.7.1.36 RX_MODE_STATUS Register (Address = 0x23) [reset = X]

RX_MODE_STATUS is described in Table 7-48.

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Table 7-48 RX_MODE_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6BC_FREQ_SELECTR/W0x0Back Channel Frequency Select
Used in conjunction with BC_HIGH_SPEED to set the back channel frequency. If BC_HIGH_SPEED = 0 then:
0: 5Mbps Back Channel
1: 10Mbps Back Channel
If BC_HIGH_SPEED = 1 then BC_FREQ_SELECT is ignored and the back channel frequency is set to 20Mbps (not available when paired with 92x serializers)
Note that changing this setting will result in some errors on the back channel for a short period of time. If set over the control channel, the Serializer should first be programmed to Auto-Ack operation (Serializer register 0x03, bit 5) to avoid a control channel timeout due to lack of response from the Deserializer.
5AUTO_I2SR/W0x1Auto I2S
Determine I2S mode from the AUX data codes.
4BC_HIGH_SPEEDR/WXBack-Channel High-Speed control
Enables high-speed back-channel at 20Mbps This bit will override the BC_FREQ_SELECT setting Note that changing this setting will result in some errors on the back channel for a short period of time. If set over the control channel, the Serializer should first be programmed to Auto-Ack operation (Serializer register 0x03, bit 5) to avoid a control channel timeout due to lack of response from the Deserializer.
BC_HIGH_SPEED is loaded from the MODE_SEL1 pin strap options.
3COAX_MODER/WXCoax Mode
Configures the FPD3 Receiver for operation over Coax or STP cabling:
0 : Shielded Twisted pair (STP)
1 : Coax
Coax Mode is loaded from the MODE_SEL1 pin strap options.
2REPEATER_MODERXRepeater Mode
Indicates device is strapped to repeater mode. Repeater Mode is loaded from the MODE_SEL1 pin strap options.
1RESERVEDR0x0Reserved
0RESERVEDR0x0Reserved

7.7.1.37 BIST_CONTROL Register (Address = 0x24) [reset = 0x8]

BIST_CONTROL is described in Table 7-49.

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Table 7-49 BIST_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-6BIST_OUT_MODER/W0x0BIST Output Mode
00 : No toggling
01 : Alternating 1/0 toggling
1x : Toggle based on BIST data
5-4AUTO_OSC_FREQR/W0x0When register 0x02 bit 5 (AUTO)CLOCK_EN) is set, this field controls the nominal frequency of the oscillator-based receive clock.
00: 50 MHz
01: 25 MHz
10: 10 MHz
11: Reserved (selects analog 25 MHz, but not for customer use)
3BIST_PIN_CONFIGR/W0x1Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through bits 2:0 in this register
2-1BIST_CLOCK_SOURCER/W0x0BIST Clock Source
This register field selects the BIST Clock Source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the Serializer after BIST is enabled. See the appropriate Serializer register descriptions for details.
0BIST_ENR/W0x0BIST Control
1: Enabled
0: Disabled

7.7.1.38 BIST_ERROR_COUNT Register (Address = 0x25) [reset = 0x0]

BIST_ERROR_COUNT is described in Table 7-50.

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Table 7-50 BIST_ERROR_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7-0BIST_ERROR_COUNTR0x0Bist Error Count
Returns BIST error count for selected port. Port selected is based on the PORT1_SEL control in the DUAL_RX_CTL register.

7.7.1.39 SCL_HIGH_TIME Register (Address = 0x26) [reset = 0x83]

SCL_HIGH_TIME is described in Table 7-51.

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Table 7-51 SCL_HIGH_TIME Register Field Descriptions
BitFieldTypeResetDescription
7-0SCL_HIGH_TIMER/W0x83I2C Controller SCL High Time
This field configures the high pulse width of the SCL output when the De-Serializer is the Controller on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 26MHz rather than the nominal 20MHz.Note: Minimum allowed value for this register is 0x07.

7.7.1.40 SCL_LOW_TIME Register (Address = 0x27) [reset = 0x84]

SCL_LOW_TIME is described in Table 7-52.

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Table 7-52 SCL_LOW_TIME Register Field Descriptions
BitFieldTypeResetDescription
7-0SCL_LOW_TIMER/W0x84I2C SCL Low Time
This field configures the low pulse width of the SCL output when the De-Serializer is the Controller on the local I2C bus. This value is also used as the SDA setup time by the I2C Target for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 26MHz rather than the nominal 20MHz.

7.7.1.41 DATAPATH_CONTROL_2 Register (Address = 0x28) [reset = 0x20]

DATAPATH_CONTROL_2 is described in Table 7-53.

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Table 7-53 DATAPATH_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
7OVERRIDE_FC_CONFIGR/W0x01: Disable loading of this register from the forward channel, keeping locally witten values intact
0: Allow forward channel loading of this register
6RESERVEDR0x0Reserved
5VIDEO_DISABLEDR/W0x1Forward channel video disabled
0 : Normal operation
1 : Video is disabled, control channel is enabled
This is a status bit indicating the forward channel is not sending active video. In this mode, the control channel and GPIO functions are enabled.
4DUAL_LINKR/W0x01: Dual-Link mode enabled
0: Single-Link mode enabled
This bit indicates whether the FPD3 serializer is in single link or dual link mode. This control is used for recovering forward channel data when the FPD3 Reciever is in auto-detect mode. To force DUAL_LINK receive mode, use the RX_PORT_SEL register (address 0x34).
3ALTERNATE_I2S_ENABLER/W0x01: Enable alternate I2S output on GPIO1 (word clock) and GPIO0 (data)
0: Normal Operation
2I2S_DISABLEDR/W0x01: I2S DISABLED
0: Normal Operation
128_BIT_VIDEOR/W0x01: 28 bit Video enable. i.e. HS, VS, DE are present in forward channel.
0: Normal Operation
0I2S_SURROUNDR/W0x01: I2S Surround enabled
0: I2S Surround disabled

7.7.1.42 FRC_CONTROL Register (Address = 0x29) [reset = 0x0]

FRC_CONTROL is described in Table 7-54.

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Table 7-54 FRC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7Timing_Mode_SelectR/W0x0Select display timing mode
0: DE only Mode
1: Sync Mode (VS,HS)
6HS_PolarityR/W0x00: Active High
1: Active Low
5VS_PolarityR/W0x00: Active High
1: Active Low
4DE_PolarityR/W0x00: Active High
1: Active Low
3FRC2_EnableR/W0x00: FRC2 disable
1: FRC2 enable
2FRC1_EnableR/W0x00: FRC1 disable
1: FRC1 enable
1Hi-FRC2_DisableR/W0x00: Hi-FRC2 enable
1: Hi-FRC2 disable
0Hi-FRC1_DisableR/W0x00: Hi-FRC1 enable
1: Hi-FRC1 disable

7.7.1.43 WHITE_BALANCE_CONTROL Register (Address = 0x2A) [reset = 0x0]

WHITE_BALANCE_CONTROL is described in Table 7-55.

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Table 7-55 WHITE_BALANCE_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-6Page_SettingR/W0x0Page setting
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
5White_Balance_EnableR/W0x00: White Balance Disable
1: White Balance Enable
4LUT_Reload_EnableR/W0x00: Reload Disable
1: Reload Enable
3RESERVEDR0x0Reserved
2RESERVEDR0x0Reserved
1-0RESERVEDR0x0Reserved

7.7.1.44 I2S_CONTROL Register (Address = 0x2B) [reset = 0x0]

I2S_CONTROL is described in Table 7-56.

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Table 7-56 I2S_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6RESERVEDR0x0Reserved
5-4RESERVEDR0x0Reserved
3I2S_FIFO_OVERRUN_STATUSR0x0I2S FIFO Overrun Status
2I2S_FIFO_UNDERRUN_STATUSR0x0I2S FIFO Underrun Status
1I2S_FIFO_ERROR_RESETR/W0x0I2S Fifo Error Reset
1: Clears FIFO Error
0I2S_DATA_FALLING_EDGER/W0x0I2S Clock Edge Select
1: I2S Data is strobed on the Rising Clock Edge.
0: I2S Data is strobed on the Falling Clock Edge.

7.7.1.45 PCLK_TEST_MODE Register (Address = 0x2E) [reset = 0x0]

PCLK_TEST_MODE is described in Table 7-57.

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Table 7-57 PCLK_TEST_MODE Register Field Descriptions
BitFieldTypeResetDescription
7EXTERNAL_PCLKR/W0x0Select pixel clock from BISTC input
6-0RESERVEDR0x0Reserved

7.7.1.46 DUAL_RX_CTL Register (Address = 0x34) [reset = 0x1]

DUAL_RX_CTL is described in Table 7-58.

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Table 7-58 DUAL_RX_CTL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6RX_LOCK_MODER/W0x0RX Lock Mode:
Determines operating conditions for indication of RX_LOCK and generation of video data.
0 : RX_LOCK asserted only when receiving active video (Forward channel VIDEO_DISABLED bit is 0)
1 : RX_LOCK asserted when device is linked to a Serializer even if active video is not being sent.
This allows indication of valid link where Bidirectional Control Channel is enabled, but Deserializer is not receiving Audio/Video data.
5RAW_2ND_BCR/W0x0Enable Raw Secondary Back channel
if this bit is set to a 1, the secondary back channel will operate in a raw mode, passing D_GPIO0 from the Deserializer to the Serializer, without any oversampling or filtering.
4-3FPD3_INPUT_MODER/W0x0FPD-Link III Input Mode
Determines operating mode of dual FPD-Link III Receive interface
00: Auto-detect based on received data
01: Forced Mode: Dual link
10: Forced Mode: Single link, primary input
11: Forced Mode: Single link, secondary input
2RESERVEDR0x0Reserved
1PORT1_SELR/W0x0Selects Port 1 for Register Access from primary I2C Address
For writes, port1 registers and shared registers will both be written.
For reads, port1 registers and shared registers will be read. This bit must be cleared to read port0 registers.
0PORT0_SELR/W0x1Selects Port 0 for Register Access from primary I2C Address
For writes, port0 registers and shared registers will both be written.
For reads, port0 registers and shared registers will be read. Note that if PORT1_SEL is also set, then port1 registers will be read.

7.7.1.47 AEQ_TEST Register (Address = 0x35) [reset = 0x0]

AEQ_TEST is described in Table 7-59.

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AEQ Test register: If PORT1_SEL is set, this register sets port1 AEQ controls.

Table 7-59 AEQ_TEST Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6AEQ_RESTARTR/W0x0Set high to restart AEQ adaptation from initial value. Method is write HIGH then write LOW - not self clearing. Adaption will be restarted on both ports.
5OVERRIDE_AEQ_FLOORR/W0x0Enable operation of SET_AEQ_FLOOR
4SET_AEQ_FLOORR/W0x0AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations
3-1RESERVEDR0x0Reserved
0RESERVEDR0x0Reserved

7.7.1.48 MODE_SEL Register (Address = 0x37) [reset = 0x0]

MODE_SEL is described in Table 7-60.

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Table 7-60 MODE_SEL Register Field Descriptions
BitFieldTypeResetDescription
7MODE_SEL1_DONER0x0MODE_SEL1 Done:
0: indicates the MODE_SEL1 decode has not been latched into the MODE_SEL1 status bits.
1: indicates the MODE_SEL1 decode has completed and latched into the MODE_SEL1 status bits.
If set, indicates the MODE_SEL1 decode has completed and latched into the MODE_SEL1 status bits.
6-4MODE_SEL1R0x0MODE_SEL1 Decode
3-bit decode from MODE_SEL1 pin, see MODE_SEL1 Table 9 first column "#" for mode selection:
000: 5 Mbps/STP (#1 on MODE_SEL1)
001: 5 Mbps/Coax (#2 on MODE_SEL1)
010: 20 Mbps/STP (#3 on MODE_SEL1)
011: 20 Mbps/Coax (#4 on MODE_SEL1)
100: 5 Mbps/STP (#5 on MODE_SEL1)
101: 5 Mbps/Coax (#6 on MODE_SEL1)
110: 20 Mbps/STP (#7 on MODE_SEL1)
111: 20 Mbps/Coax (#8 on MODE_SEL1)
Note: 0x37[6] is the MSB; 0x37[4] is the LSB
3MODE_SEL0_DONER0x0MODE_SEL0 Done:
0: indicates the MODE_SEL0 decode has not been latched into the MODE_SEL0 status bits.
1: indicates the MODE_SEL0 decode has completed and latched into the MODE_SEL0 status bits.
If set, indicates the MODE_SEL0 decode has completed and latched into the MODE_SEL0 status bits.
2-0MODE_SEL0R0x0MODE_SEL0 Decode
3-bit decode from MODE_SEL0 pin, see MODE_SEL0 in Table 8 first column "#" for mode selection:
000: Dual OLDI output (#1 on MODE_SEL0)
001: Dual SWAP output (#2 on MODE_SEL0)
010: Single OLDI output (#3 on MODE_SEL0)
011: Replicate (#4 on MODE_SEL0)
100: Dual OLDI output (#5 on MODE_SEL0)
101: Dual SWAP output (#6 on MODE_SEL0)
110: Single OLDI output (#7 on MODE_SEL0)
111: Replicate (#8 on MODE_SEL0)
Note: 0x37[2] is the MSB; 0x37[0] is the LSB

7.7.1.49 I2S_DIVSEL Register (Address = 0x3A) [reset = 0x0]

I2S_DIVSEL is described in Table 7-61.

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Table 7-61 I2S_DIVSEL Register Field Descriptions
BitFieldTypeResetDescription
7reg_ov_mdivR/W0x00: No override for MCLK divider
1: Override divider select for MCLK
6-4reg_mdivR/W0x0Divide ratio select for VCO output (32*REF/M)
000: Divide by 32 (=REF/M)
001: Divide by 16 (=2*REF/M)
010: Divide by 8 (=4*REF/M)
011: Divide by 4 (=8*REF/M)
100,
101: Divide by 2 (=16*REF/M)
110,
111: Divide by 1 (32*REF/M)
3RESERVEDR0x0Reserved
2reg_ov_mselectR/W0x00: Divide ratio of reference clock VCO selected by PLL-SM
1: Override divide ratio of clock to VCO
1-0reg_mselectR/W0x0Divide ratio select for VCO input (M)
00: Divide by 1
01: Divide by 2
10: Divide by 4
11: Divide by 8

7.7.1.50 EQ_STATUS Register (Address = 0x3B) [reset = 0x0]

EQ_STATUS is described in Table 7-62.

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Equalizer Status register: If PORT1_SEL is set, this register returns port1 status.

Table 7-62 EQ_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0Reserved
5-0EQ_statusR0x0EQ Status - setting direct to analog
If Adaptive EQ is bypassed, these values are the {EQ2, EQ1} settings from the ADAPTIVE EQ BYPASS register (0x44). If Adaptive EQ is enabled, the EQ status is determined by the adaptive Equalizer.

7.7.1.52 HSCC_CONTROL Register (Address = 0x43) [reset = 0x0]

HSCC_CONTROL is described in Table 7-64.

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Table 7-64 HSCC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0Reserved
4SPI_POCI_MODER/W0x0SPI POCI pin mode during Reverse SPI mode During Reverse SPI mode, SPI_POCI is typically an output signal. For bused SPI applications, it may be necessary to tri-state the SPI_POCI output if the device is not selected (SPI_CS = 0).
0 : Always enable SPI_POCI output driver
1 : Tri-state SPI_POCI output if SPI_CS is not asserted (low)
3SPI_CPOLR/W0x0SPI Clock Polarity Control
0 : SPI Data driven on Falling clock edge, sampled on Rising clock edge
1 : SPI Data driven on Rising clock edge, sampled on Falling clock edge
2-0HSCC_MODER/W0x0High-Speed Control Channel Mode Enables high-speed modes for the secondary link back-channel, allowing higher speed signaling of GPIOs or SPI interface:
These bits indicates the High Speed Control Channel mode of operation:
000: Normal frame, GPIO mode
001: High Speed GPIO mode, 1 GPIO
010: High Speed GPIO mode, 2 GPIOs
011: High Speed GPIO mode: 4 GPIOs
100: Reserved
101: Reserved
110: High Speed, Forward Channel SPI mode
111: High Speed, Reverse Channel SPI mode

7.7.1.53 ADAPTIVE_EQ_BYPASS Register (Address = 0x44) [reset = 0x60]

ADAPTIVE_EQ_BYPASS is described in Table 7-65.

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Adaptive Equalizer Bypass register: If PORT1_SEL is set, this register sets port1 AEQ controls.

Table 7-65 ADAPTIVE_EQ_BYPASS Register Field Descriptions
BitFieldTypeResetDescription
7-5EQ_STAGE_1_SELECT_VALUER/W0x3EQ select value[2:0] - Used if adaptive EQ is bypassed. When ADAPTIVE_EQ_BYPASS is set to 1, these bits will be reflected in EQ Status[2:0] (register 0x3B)
4RESERVEDR0x0Reserved
3-1EQ_STAGE_2_SELECT_VALUER/W0x0EQ select value[5:3] - Used if adaptive EQ is bypassed. When ADAPTIVE_EQ_BYPASS is set to 1, these bits will be reflected in EQ Status[5:3] (register 0x3B)
0ADAPTIVE_EQ_BYPASSR/W0x01: Disable adaptive EQ
0: Enable adaptive EQ

7.7.1.54 ADAPTIVE_EQ_MIN_MAX Register (Address = 0x45) [reset = 0x8]

ADAPTIVE_EQ_MIN_MAX is described in Table 7-66.

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Note: If PORT1_SEL is set, this register sets port1 AEQ_FLOOR value. AEQ_FLOOR readback is only available on port0, that means writes to the port1 setting will still work but the written value can not be read back.

Table 7-66 ADAPTIVE_EQ_MIN_MAX Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0x100Reserved
4RESERVEDR/W0x0Reserved
3-0ADAPTIVE_EQ_FLOOR_VALUER/W0x8When AEQ floor is enabled byregister {reg_35[5:4]} the starting setting is given by this register.

7.7.1.55 FPD_TX_MODE Register (Address = 0x49) [reset = X]

FPD_TX_MODE is described in Table 7-67.

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Table 7-67 FPD_TX_MODE Register Field Descriptions
BitFieldTypeResetDescription
7MAPSEL_MODERXMapsel Pin Status
Strap option on the MODE_SEL0 pin
6MAPSEL_OVER_WRITER/W0x0Mapsel Over Write enable from register configuration
5MAPSEL_REG_BITR/W0x0Register setting of MAPSEL mode if MAPSEL OVER WRITE is set
4-2RESERVEDR0x0Reserved
1-0FPD_OUT_MODER/WXFPD/OLDI output mode
Controls single/dual operation of the FPD Transmit ports
00 : Dual FPD/OLDI output
01 : Dual SWAP FPD/OLDI output
10 : Single FPD/OLDI output
11 : Replicate FPD/OLDI output
The FPD_OUT_MODE register bits are loaded at reset from the MODE_SEL0 pin strap options.

7.7.1.56 LVDS_CONTROL Register (Address = 0x4B) [reset = 0x0]

LVDS_CONTROL is described in Table 7-68.

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Table 7-68 LVDS_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0x0Reserved
5-4RESERVEDR/W0x0Reserved
3-2RESERVEDR/W0x10Reserved
1-0LVDS_VOD_ControlR/W0x0FPD/OLDI Output VOD Setting
00: Setting 1 - 190mV typical voltage swing (single-ended)
01: Setting 2 - 275mV typical voltage swing (single-ended)
10: Setting 3 - 325mV typical voltage swing (single-ended)
11: Setting 4 - 375mV typical voltage swing (single-ended).Note: Changing this value for Port1 requires selecting Port1 in reg 0x34.

7.7.1.57 CML_OUTPUT_CTL1 Register (Address = 0x52) [reset = 0x0]

CML_OUTPUT_CTL1 is described in Table 7-69.

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Table 7-69 CML_OUTPUT_CTL1 Register Field Descriptions
BitFieldTypeResetDescription
7CML_Channel_Select_1R/W0x0Selects between PORT0 and PORT1 to output onto CMLOUT±.
0: Recovered forward channel data from RIN0± is output on CMLOUT±
1: Recovered forward channel data from RIN1± is output on CMLOUT±
CMLOUT driver must be enabled by setting 0x56[3] = 1. Note: This bit must match 0x57[2:1] setting for PORT0 or PORT1.
6RESERVEDR0x0Reserved
5-2RESERVEDR0x0Reserved
1-0RESERVEDR0x0Reserved

7.7.1.58 CML_OUTPUT_ENABLE Register (Address = 0x56) [reset = 0x0]

CML_OUTPUT_ENABLE is described in Table 7-70.

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Table 7-70 CML_OUTPUT_ENABLE Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0Reserved
4RESERVEDR0x0Reserved
3CML_Output_EnableR/W0x0Enable CMLOUT± Loop-through Driver
0: Disabled (Default)
1: Enabled
2-1RESERVEDR0x0Reserved
0RESERVEDR0x0Reserved

7.7.1.59 CML_OUTPUT_CTL2 Register (Address = 0x57) [reset = 0x0]

CML_OUTPUT_CTL2 is described in Table 7-71.

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Table 7-71 CML_OUTPUT_CTL2 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0x0Reserved
2-1CML_CHANNEL_SELECT_2R/W0x0Selects between PORT0 and PORT1 to output onto CMLOUT±.
01: Recovered forward channel data from RIN0± is output on CMLOUT±
10: Recovered forward channel data from RIN1± is output on CMLOUT±
CMLOUT driver must be enabled by setting 0x56[3] = 1. Note: This must match 0x52[7] setting for PORT0 or PORT1.Note: Due to internal routing differences between CMLOUT0 and CMLOUT1 inside the device, CMLOUT1 monitor may show significantly degraded performance when compared to CMLOUT0, especially at high PCLK frequency. This does not necessarily indicate an issue with the true channel performance.
0RESERVEDR0x0Reserved

7.7.1.60 CML_OUTPUT_CTL3 Register (Address = 0x63) [reset = 0x0]

CML_OUTPUT_CTL3 is described in Table 7-72.

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Table 7-72 CML_OUTPUT_CTL3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0Reserved
5RESERVEDR0x0Reserved
4RESERVEDR0x0Reserved
3RESERVEDR0x0Reserved
2RESERVEDR0x0Reserved
1RESERVEDR0x0Reserved
0CML_TX_PWDNR/W0x0Powerdown CML TX
0: CML TX powered up
1: CML TX powered down
NOTE: CML TX must be powered down prior to enabling Pattern Generator.

7.7.1.61 PGCTL Register (Address = 0x64) [reset = 0x10]

PGCTL is described in Table 7-73.

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Table 7-73 PGCTL Register Field Descriptions
BitFieldTypeResetDescription
7-4PATGEN_SELR/W0x1Fixed Pattern Select:
This field selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. The following table shows the color selections in non-inverted followed by inverted color mode:

0000: Reserved
0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/White to Cyan
1000: Horizontally Scaled Black to Green/White to Magenta
1001: Horizontally Scaled Black to Blue/White to Yellow
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/White to Cyan
1100: Vertically Scaled Black to Green/White to Magenta
1101: Vertically Scaled Black to Blue/White to Yellow
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers
1111: Reserved
3PATGEN_UNHR/W0x0Enables the UNH-IOL compliance test pattern:
0: Pattern type selected by PATGEN_SEL
1: Compliance test pattern is selected. Value of PATGEN_SEL is ignored.
2PATGEN_COLOR_BARSR/W0x0Enable Color Bars:
0: Color Bars disabled
1: Color Bars enabled (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black)
1PATGEN_VCOM_REVR/W0x0Reverse order of color bands in VCOM pattern:
0: Color sequence from top left is (Yellow, Cyan, Blue, Red)
1: Color sequence from top left is (Blue, Cyan, Yellow, Red)
0PATGEN_ENR/W0x0Pattern Generator Enable:
1: Enable Pattern Generator
0: Disable Pattern Generator
NOTE: CML TX must be powered down prior to enabling Pattern Generator by setting register bit 0x63[0]=1.

7.7.1.62 PGCFG Register (Address = 0x65) [reset = 0x0]

PGCFG is described in Table 7-74.

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Table 7-74 PGCFG Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0Reserved
4PATGEN_18BR/W0x018-bit Mode Select:
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness.
3PATGEN_EXTCLKR/W0x0Select External Clock Source:
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing

This bit has no effect in external timing mode (PATGEN_TSEL = 0).
2PATGEN_TSELR/W0x0Timing Select Control:
1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size, Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
0: the Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals.
1PATGEN_INVR/W0x0Enable Inverted Color Patterns:
1: Invert the color output.
0: Do not invert the color output.
0PATGEN_ASCRLR/W0x0Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.

7.7.1.63 PGIA Register (Address = 0x66) [reset = 0x0]

PGIA is described in Table 7-75.

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Table 7-75 PGIA Register Field Descriptions
BitFieldTypeResetDescription
7-0PATGEN_IAR/W0x0Indirect Address:
This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register.

7.7.1.64 PGID Register (Address = 0x67) [reset = 0x0]

PGID is described in Table 7-76.

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Table 7-76 PGID Register Field Descriptions
BitFieldTypeResetDescription
7-0PATGEN_IDR/W0x0Indirect Data:
When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the readback value.

7.7.1.65 PGDBG Register (Address = 0x68) [reset = 0x0]

PGDBG is described in Table 7-77.

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Table 7-77 PGDBG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0Reserved
3PATGEN_BIST_ENR/W0x0Pattern Generator BIST Enable:
Enables Pattern Generator in BIST mode. Pattern Generator will compare received video data with local generated pattern. Upstream device must be programmed to the same pattern.
2RESERVEDR0x0Reserved
1RESERVEDR0x0Reserved
0RESERVEDR0x0Reserved

7.7.1.66 PGTSTDAT Register (Address = 0x69) [reset = 0x0]

PGTSTDAT is described in Table 7-78.

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Table 7-78 PGTSTDAT Register Field Descriptions
BitFieldTypeResetDescription
7PATGEN_BIST_ERRR0x0Pattern Generator BIST Error Flag
During Pattern Generator BIST mode, this bit indicates if the BIST engine has detected errors. If the BIST Error Count (available in the Pattern Generator indirect registers) is non-zero, this flag will be set.
6RESERVEDR0x0Reserved
5-0RESERVEDR0x0Reserved

7.7.1.67 GPI_PIN_STATUS_1 Register (Address = 0x6E) [reset = 0x0]

GPI_PIN_STATUS_1 is described in Table 7-79.

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Table 7-79 GPI_PIN_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
7GPI7_Pin_StatusR0x0GPI7/I2S_WC pin status
6GPI6_Pin_StatusR0x0GPI6/I2S_DA pin status
5GPI5_Pin_StatusR0x0GPI5/I2S_DB pin status
4RESERVEDR0x0Reserved
3GPI3_Pin_StatusR0x0GPI3 / I2S_DD pin status
2GPI2_Pin_StatusR0x0GPI2 / I2S_DC pin status
1GPI1_Pin_StatusR0x0GPI1 pin status
0GPI0_Pin_StatusR0x0GPI0 pin status

7.7.1.68 GPI_PIN_STATUS_2 Register (Address = 0x6F) [reset = 0x0]

GPI_PIN_STATUS_2 is described in Table 7-80.

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Table 7-80 GPI_PIN_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0Reserved
0GPI8_Pin_StatusR0x0GPI8/I2S_CLK pin status

7.7.1.69 RX_ID0 Register (Address = 0xF0) [reset = 0x5F]

RX_ID0 is described in Table 7-81.

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Table 7-81 RX_ID0 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID0R0x5FRX_ID0: First byte ID code, '_ '

7.7.1.70 RX_ID1 Register (Address = 0xF1) [reset = 0x55]

RX_ID1 is described in Table 7-82.

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Table 7-82 RX_ID1 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID1R0x55RX_ID1: 2nd byte of ID code, 'U '

7.7.1.71 RX_ID2 Register (Address = 0xF2) [reset = 0x48]

RX_ID2 is described in Table 7-83.

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Table 7-83 RX_ID2 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID2R0x48RX_ID2: 3rd byte of ID code. Value will be either 'B ' or 'H '. 'H ' indicates an HDCP capable device.

7.7.1.72 RX_ID3 Register (Address = 0xF3) [reset = 0x39]

RX_ID3 is described in Table 7-84.

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Table 7-84 RX_ID3 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID3R0x39RX_ID3: 4th byte of ID code: '9 '

7.7.1.73 RX_ID4 Register (Address = 0xF4) [reset = 0x34]

RX_ID4 is described in Table 7-85.

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Table 7-85 RX_ID4 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID4R0x34RX_ID4: 5th byte of ID code.

7.7.1.74 RX_ID5 Register (Address = 0xF5) [reset = 0x38]

RX_ID5 is described in Table 7-86.

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Table 7-86 RX_ID5 Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_ID5R0x38RX_ID5: 6th byte of ID code.