ZHCSR80A June   2009  – January 2023 AMC6821-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 ADC Converter
      2. 8.2.2 Temperature Sensor
        1. 8.2.2.1 Series Resistance Cancellation
        2. 8.2.2.2 Reading Temperature Data
        3. 8.2.2.3 Temperature Out-of-Range Detection
        4. 8.2.2.4 Remote Temperature Sensor Failure Detection
      3. 8.2.3 PWM Output
      4. 8.2.4 PWM Waveform Setting
      5. 8.2.5 Fan Speed Measurement
        1. 8.2.5.1 Tach-Data Register
          1. 8.2.5.1.1 Reading the Tach Data Register
          2. 8.2.5.1.2 RPM Measurement Rate
          3. 8.2.5.1.3 Select Number of Pulses/Revolution
          4. 8.2.5.1.4 Tach Mode Selection
          5. 8.2.5.1.5 Fan RPM Out-of-Range Detection
      6. 8.2.6 Fan Failure Detection
      7. 8.2.7 FAN-FAULT Pin
      8. 8.2.8 Fan Control
        1. 8.2.8.1 THERM Pin and External Hardware Control
          1. 8.2.8.1.1 THERM Pin as an Output
          2. 8.2.8.1.2 THERM Pin as an Input
        2. 8.2.8.2 Fan Spin-Up
        3. 8.2.8.3 Normal Fan Speed Control
          1. 8.2.8.3.1 Software DCY Control Mode
          2. 8.2.8.3.2 Software-RPM Control Mode (Fan Speed Regulator)
          3. 8.2.8.3.3 Auto Temperature Fan Mode
      9. 8.2.9 Interrupt
        1. 8.2.9.1 OVR Pin
        2. 8.2.9.2 SMBALERT Pin
        3. 8.2.9.3 SMBALERT Interrupt Behavior
        4. 8.2.9.4 Handling SMBALERT Interrupts
    3. 8.3 Device Functional Modes
    4. 8.4 Programming
      1. 8.4.1 SMBus Interface
        1. 8.4.1.1 Communication Protocols
      2. 8.4.2 SMBus Alert Response Address (ARA)
      3. 8.4.3 Power-On Reset and Start Operation
    5. 8.5 Register Map
      1. 8.5.1 Register Description
        1. 8.5.1.1 Device Configuration Registers
        2. 8.5.1.2 Device Status Registers
        3. 8.5.1.3 Fan Controller Registers
        4. 8.5.1.4 Temperature Data Registers
        5. 8.5.1.5 Temperature Limit Registers
          1. 8.5.1.5.1 Tach-Data Register
          2. 8.5.1.5.2 Tach Setting Register
          3. 8.5.1.5.3 Tach Low Limit Register
          4. 8.5.1.5.4 Tach High Limit Register
  9. 9 Application and Implementation
    1. 9.1 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.2.9.4 Handling SMBALERT Interrupts

To prevent the system from being tied up while servicing interrupts, it is recommend to handle the SMBALERT interrupt in this manner:

  1. Detect the SMBALERT assertion.
  2. Enter the interrupt handler.
  3. Read the status registers to identify the interrupt source.
  4. Disable the interrupt source by clearing the appropriate enable bit in the configuration registers.
  5. Take the appropriate action for a given interrupt source.
  6. Exit the interrupt handler.
  7. Periodically poll the status registers. If the interrupt source bit has cleared, reset the corresponding interrupt enable bit to '1'. This reset makes the SMBALERT output and status bits behave as shown in Figure 8-22.

GUID-86DC9C4C-87D2-4CC6-A988-D0C0060D10AC-low.gifFigure 8-22 How Masking the Interrupt Source Affects SMBALERT

Individual interrupts can be masked by clearing the corresponding interrupt enable bit in the configuration registers to prevent SMBALERT interrupts. Note that masking an interrupt source only prevents the SMBALERT pin output from being asserted; the appropriate status bit gets set as normal.

GUID-01C1FAFD-A57F-4290-86AE-902EA6ED4373-low.gifFigure 8-23 SMBALERT