ZHCSAM3B December   2012  – April 2022 ADS54T01

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Test Pattern Output
      2. 8.3.2  Clock Inputs
      3. 8.3.3  SNR and Clock Jitter
      4. 8.3.4  Analog Inputs
      5. 8.3.5  Over-Range Indication
      6. 8.3.6  Interleaving Correction
      7. 8.3.7  High-Resolution Output Data
      8. 8.3.8  Low-Resolution Output Data
      9. 8.3.9  Full Speed – 7 Bit
      10. 8.3.10 Decimated Low-Resolution Output Data
      11. 8.3.11 Multi Device Synchronization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Feedback Mode: Burst Mode
      3. 8.4.3 Receive Mode: Decimation Filter
      4. 8.4.4 Manual Trigger Mode
      5. 8.4.5 Auto Trigger Mode
    5. 8.5 Programming
      1. 8.5.1 Device Initialization
      2. 8.5.2 Serial Register Write
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Interface Registers
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.5.3 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

  1. Drive SDENB pin low
  2. Set the RW bit (A7) to "1". This setting disables any further writes to the registers
  3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be read.
  4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin
  5. The external controller can latch the contents at the SCLK rising edge.
  6. To enable register writes, reset the RW register bit to "0".
GUID-328C9535-FA30-41D7-850E-B8F91EDDF48F-low.gifFigure 8-21 Serial Register Read Timing Diagram