ZHCSAM3B December   2012  – April 2022 ADS54T01

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Test Pattern Output
      2. 8.3.2  Clock Inputs
      3. 8.3.3  SNR and Clock Jitter
      4. 8.3.4  Analog Inputs
      5. 8.3.5  Over-Range Indication
      6. 8.3.6  Interleaving Correction
      7. 8.3.7  High-Resolution Output Data
      8. 8.3.8  Low-Resolution Output Data
      9. 8.3.9  Full Speed – 7 Bit
      10. 8.3.10 Decimated Low-Resolution Output Data
      11. 8.3.11 Multi Device Synchronization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Feedback Mode: Burst Mode
      3. 8.4.3 Receive Mode: Decimation Filter
      4. 8.4.4 Manual Trigger Mode
      5. 8.4.5 Auto Trigger Mode
    5. 8.5 Programming
      1. 8.5.1 Device Initialization
      2. 8.5.2 Serial Register Write
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Interface Registers
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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7.9 Electrical Characteristics

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V
PARAMETERTEST CONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
High-level input voltageAll digital inputs support 1.8-V and 3.3-V logic levels.0.7 x IOVDDV
Low-level input voltage0.3 x IOVDDV
High-level input current–50200µA
Low-level input current–5050µA
Input capacitance5pF
DIGITAL OUTPUTS – SDO
High-level output voltageIload = -100 µAIOVDD – 0.2V
Iload = -2 mA0.8 x IOVDD
Low-level output voltageIload = 100 µA0.2V
Iload = 2 mA0.22 x IOVDD
DIGITAL INPUTS – SYNCP/N, TRIGGERP/N
VIDDifferential input voltage250350450mV
VCMInput common-mode voltage1.1251.21.375V
tSU500ps
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N
VODOutput differential voltageIout = 3.5 mA250350450mV
VOCMOutput common-mode voltageIout = 3.5 mA1.1251.251.375V
tsuFs = 750 MspsData valid to zero-crossing of DACLK320400ps
thFs = 750 MspsZero-crossing of DACLK to data becoming invalid250320ps
tPDFs = 750MspsCLKIN falling edge to DACLK rising edge3.363.693.92ns
tRISE10% - 90%100150200ps
tFALL90% - 10%100150200ps
GUID-37B74DC5-4454-4F73-86DF-08CA19351D7E-low.gifFigure 7-1 Timing Diagram for 12-Bit DDR Output