ZHCSAM3B December   2012  – April 2022 ADS54T01

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Test Pattern Output
      2. 8.3.2  Clock Inputs
      3. 8.3.3  SNR and Clock Jitter
      4. 8.3.4  Analog Inputs
      5. 8.3.5  Over-Range Indication
      6. 8.3.6  Interleaving Correction
      7. 8.3.7  High-Resolution Output Data
      8. 8.3.8  Low-Resolution Output Data
      9. 8.3.9  Full Speed – 7 Bit
      10. 8.3.10 Decimated Low-Resolution Output Data
      11. 8.3.11 Multi Device Synchronization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Feedback Mode: Burst Mode
      3. 8.4.3 Receive Mode: Decimation Filter
      4. 8.4.4 Manual Trigger Mode
      5. 8.4.5 Auto Trigger Mode
    5. 8.5 Programming
      1. 8.5.1 Device Initialization
      2. 8.5.2 Serial Register Write
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Interface Registers
  9. Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Pin Configuration and Functions

GUID-21489039-9B49-4126-BA0B-722D2971F16C-low.gifFigure 6-1 ADS54T01 ZAY Package, 196-Pin NFBGA, Top View (DDR Output Mode)
Table 6-1 Pin Functions
PINI/O TYPE(1)DESCRIPTION
NAMENUMBER
INPUT/REFERENCE
INA_P/NK14, L14IAnalog ADC differential input signal.
VCMB14OOutput of the analog input common mode (nominally 1.9 V). A 0.1-μF capacitor to AGND is recommended, but not required.
VREFA14IReference voltage input. A 0.1-μF capacitor to AGND is recommended.
CLOCK/SYNC
CLKINP/NP14, P13IDifferential input clock
SYNCP/NP9, N9ISynchronization input. Inactive if logic low. When clocked in a high state initially, this is used for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100-Ω termination.
CONTROL/SERIAL
SRESETB12ISerial interface reset input. Active low. Initialized internal registers during high-to-low transition. Asynchronous. Internal 50-kΩ pullup resistor to IOVDD.
ENABLEB11IChip enable – active high. Power-down function can be controlled through SPI register assignment. Internal 50-kΩ pullup resistor to IOVDD.
SCLKA12ISerial interface clock. Internal 50-kΩ pulldown resistor.
SDIOA11I/OBidirectional serial data in 3-pin mode (default). In 4-pin interface mode (register x00, D16), the SDIO pin in an input only. Internal 50-kΩ pulldown resistor.
SDENBA13ISerial interface enable. Internal 50-kΩ pulldown resistor.
SDOA10OUni-directional serial interface data in 4-pin mode (register x00, D16). The SDO pin is tri-stated in 3-pin interface mode (default). Internal 50-kΩ pulldown resistor.
DATA INTERFACE
DA[11:0]P/NP3, N3, P2, N2, P1, N1, M4, M3, M2, M1, L4, L3, L2, L1, K4, K3, K2, K1, J4, J3, J2, J1, H4, H3OADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.
DACLKP/NH2, H1ODDR differential output data clock for Bus A. Register programmable to provide either rising or falling edge to center of stable data nominal timing.
SYNCOUTP/NP5, N5OSynchronization output signal for synchronizing multiple ADCs. Can be disabled through the SPI.
OVRAP/NM5, L5OBus A, Overrange indicator, LVDS output. A logic high signals an analog input in excess of the full-scale range. Optional SYNC output.
TRIGGERP/NP10, N10ITrigger used for high-resolution output data in feedback mode. Internal 100-Ω termination.
TRDYP/NP7, N7OTrigger ready output indicator
HRESP/NP6, N6OIndicator for high-resolution output data; logic high signals 12-bit output data.
NO CONNECT
NCA1, A2, A3, A4, A5, A6, A7, B1, B2, B3, B4, B5, B6, B7, C1, C2, C3, C4, C5, D1, D2, D3, D4, D5, D14, E1, E2, E3, E4, E14, F1, F2, F3, F4, G1, G2, G3, G4, N4, P4Do not connect to pin, leave floating.
TESTMODEB13Used for factory internal test. Do not connect to pin, leave floating.
POWER SUPPLY
AVDD33D12, E12, F12, G12, H12, J12, K12, L12, N12, P12P3.3-V analog supply
AVDDCG14, H14P1.8-V supply for clock input
AVDD18D10, D11, E11, F11, G11, H11, J11, K11, L10, L11, N11, P11P1.8-V analog supply
DVDDA8, A9, B8, B9, C8, D8, L8, M8, N8, P8P1.8-V supply for digital block
DVDDLVDSC6, C7, D6, D7, L6, L7, M6, M7P1.8-V supply for LVDS outputs
IOVDDB10P1.8-V for digital I/Os
GNDC9, C10, C11, C12, C13, C14, D9, D13, E5, E6, E7, E8, E9, E10, E13, F5, F6, F7, F8, F9, F10, F13, F14, G5, G6, G7, G8, G9, G10,H5, H6, H7, H8, H9, H10, J5, J6, J7, J8, J9, J10, K5, K6, K7, K8, K9, K10, L9, M9, M10, M11, M12, M13, M14,N13, N14GNDGround
The definitions below define the I/O type for each pin.
  • I = Input
  • O = Output
  • I/O = Input / Output
  • P = Power Supply
  • G = Ground