SN74AUP1G14
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typical at 3.3 V) - Low Input Capacitance (CI = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Includes Schmitt-Trigger Inputs
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.9 ns Maximum at 3.3 V
The AUP family is TIs premier solution to the industrys low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
您可能會感興趣的類似產品
針腳對針腳的功能與所比較的裝置相同。
功能相似於所比較的產品。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74AUP1G14 Low-Power Single Schmitt-Trigger Inverter datasheet (Rev. J) | PDF | HTML | 2017/11/2 | ||
| Application brief | Understanding Schmitt Triggers (Rev. B) | PDF | HTML | 2025/4/17 | |||
| 應用說明 | Designing and Manufacturing with TI's X2SON Packages | 2017/8/23 | ||||
| 白皮書 | Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) | 2017/5/1 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM
支援任何具 DTT、DRY、DPW、DTM、DQE、DQM、DSF 或 DTQ 封裝的邏輯或轉換裝置之通用 EVM。可實現靈活評估的電路板設計。
TIDA-00377 — 採用 MOSFET 的自我供電 AC 固態繼電器參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-5X3 (DRL) | 5 | Ultra Librarian |
| X2SON (DSF) | 6 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
| DSBGA (YFP) | 4 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
| X2SON (DPW) | 5 | Ultra Librarian |
| USON (DRY) | 6 | Ultra Librarian |