SN74LVC1G14
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD protection exceeds JESD 22
- 2000V human-body model (A114-A)
- 200V machine model (A115-A)
- 1000V charged-device model (C101)
- Available in the Texas Instruments NanoFree™ package
- Supports 5V VCC operation
- Inputs accept voltages to 5.5V
- Maximum tpd of 4.6ns at 3.3V
- Low power consumption, 10µA maximum ICC
- ±24mA output drive at 3.3V
- Ioff supports partial-power-down mode operation
This single Schmitt-trigger inverter is designed for 1.65V to 5.5V VCC operation.
The SN74LVC1G14 device contains one inverter and performs the Boolean function Y = A. The device functions as an independent inverter with Schmitt-trigger inputs, so the device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals to provide hysteresis (ΔVT) which makes the device tolerant to slow or noisy input signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LVC1G14 Single Schmitt-Trigger Inverter datasheet (Rev. AA) | PDF | HTML | 2025/10/28 | ||
| Application brief | Understanding Schmitt Triggers (Rev. B) | PDF | HTML | 2025/4/17 | |||
| Product overview | Generate an Enable Signal that can be Toggled | PDF | HTML | 2023/6/14 | |||
| Product overview | Generate a Power-On Reset Pulse | PDF | HTML | 2023/6/14 | |||
| Application brief | Enabling Optimal Solar Inverter Power Stage Designs with Logic | PDF | HTML | 2021/8/17 | |||
| 應用說明 | Designing and Manufacturing with TI's X2SON Packages | 2017/8/23 | ||||
| 白皮書 | Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) | 2017/5/1 | ||||
| 應用說明 | Use of the CMOS Unbuffered Inverter in Oscillator Circuits | 2003/11/6 |
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM
支援任何具 DTT、DRY、DPW、DTM、DQE、DQM、DSF 或 DTQ 封裝的邏輯或轉換裝置之通用 EVM。可實現靈活評估的電路板設計。
許多 TI 參考設計包含 SN74LVC1G14
使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| X2SON (DSF) | 6 | Ultra Librarian |
| SOT-5X3 (DRL) | 5 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
| DSBGA (YZV) | 4 | Ultra Librarian |
| DSBGA (YZP) | 5 | Ultra Librarian |
| USON (DRY) | 6 | Ultra Librarian |
| X2SON (DPW) | 5 | Ultra Librarian |