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SN74AUP1G08

現行

1 通道、2 輸入、0.8V 至 3.6V 低功耗 (< 1uA) AND 閘

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產品規格表

SN74AUP1G08

現行
產品規格表 立即訂購

產品詳細資料

Technology family AUP Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) DSBGA (YFP) 6 1.4000000000000001 mm² (— mm × — mm) DSBGA (YZP) 5 2.1875 mm² (— mm × — mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm)
  • Available in the Ultra Small 0.64mm2 Package (DPW) With 0.5mm Pitch
  • Low Static-Power Consumption: ICC = 0.9µA Maximum
  • Low Dynamic-Power Consumption: Cpd = 4.3pF Typical at 3.3V
  • Low Input Capacitance: Ci = 1.5pF Typical
  • Low Noise: Overshoot and Undershoot <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3V)
  • Wide Operating VCC Range of 0.8V to 3.6V
  • Optimized for 3.3V Operation
  • 3.6V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.3ns Maximum at 3.3V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000V Human-Body Model (A114-B, Class II)
    • 1000V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64mm2 Package (DPW) With 0.5mm Pitch
  • Low Static-Power Consumption: ICC = 0.9µA Maximum
  • Low Dynamic-Power Consumption: Cpd = 4.3pF Typical at 3.3V
  • Low Input Capacitance: Ci = 1.5pF Typical
  • Low Noise: Overshoot and Undershoot <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3V)
  • Wide Operating VCC Range of 0.8V to 3.6V
  • Optimized for 3.3V Operation
  • 3.6V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.3ns Maximum at 3.3V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000V Human-Body Model (A114-B, Class II)
    • 1000V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A • B or Y = /A + /B in positive logic.

This single 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A • B or Y = /A + /B in positive logic.
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SN74LVC1G11 現行 1 通道、3 輸入、1.65V 至 5.5V 32mA 驅動強度 AND 閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G373 現行 具有 3S 輸出的單 D 型鎖存 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
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SN74LVC1G18 現行 具有 3 態淘汰輸出的二選一非反相解多工器 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G10 現行 單路 3 輸入、1.65-V 至 5.5-V NAND 閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G332 現行 1 通道、3 輸入、1.65-V 至 5.5-V 32-mA 驅動強度 OR 閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74AHC1G08 現行 1 通道、2 輸入、2-V 至 5.5-V 高速 (9 ns) AND 閘 Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA
SN74LVC1G08 現行 1 通道、2 輸入、1.65V 至 5.5V 32mA 驅動強度 AND 閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G27 現行 單路 3 輸入、1.65-V 至 5.5-V NOR 閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AUP1G08 Low-Power Single 2-Input Positive-AND Gate datasheet (Rev. Q) PDF | HTML 2024/3/1
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025/4/17
Application brief Optimizing Industrial Robot CPU Boards with Logic and Voltage Translation PDF | HTML 2022/12/12
Application brief Optimizing WLAN and WiFi Access Point Systems With Logic and Voltage Translation PDF | HTML 2022/11/3
應用說明 Designing and Manufacturing with TI's X2SON Packages 2017/8/23

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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
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5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM

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模擬型號

SN74AUP1G08 Behavioral SPICE Model

SCEM690.ZIP (7 KB) - PSpice 模型
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模擬型號

SN74AUP1G08 IBIS Model (Rev. A)

SCEM405 (361 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
DSBGA (YFP) 6 Ultra Librarian
DSBGA (YZP) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
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