TVP7002
- Analog Channels
- –6-dB to 6-dB Analog Gain
- Analog Input Multiplexers (MUXs)
- Automatic Video Clamp
- Three Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)
- Clamping: Selectable Clamping Between Bottom Level and Mid Level
- Offset: 1024-Step Programmable RGB or YPbPr Offset Control
- Gain: 8-Bit Programmable Gain Control
- ADC: 8-/10-Bit 165-/110-MSPS ADC
- Automatic Level Control (ALC) Circuit
- Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
- Support for DC- and AC-Coupled Input Signals
- Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
- Supports PC Graphics Inputs up to UXGA Programmable RGB-to-YCbCr Color Space Conversion
- Horizontal PLL
- Fully Integrated Horizontal PLL for Pixel Clock Generation
- 12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
- Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
- 5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
- Output Formatter
- Supports 20-bit 4:2:2 Outputs With Embedded Syncs
- Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
- Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output Data
- System
- Industry-Standard Normal/Fast I2C Interface With Register Readback Capability
- Space-Saving 100-Pin TQFP Package
- Thermally-Enhanced PowerPAD Package for Better Heat Dissipation
The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.
The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.
TI 不提供设计支持
TI 不会为该产品的新工程（例如新内容或软件更新）提供持续的设计支持。如可用，您将在产品文件夹中找到相关的配套资料、软件和工具。您也可以在 TI E2ETM 支持论坛中搜索已归档的信息。
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | TVP7002 Triple 8/10-Bit 165/110-MSPS Video and Graphics Digitizer With Horiz PLL 数据表 (Rev. C) | 2013-4-24 | |||
| 应用手册 | TVP7002 PCB Layout Guidelines | 2010-6-16 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
TMDXEVM368 — TMS320DM36x 评估模块
借助 TMS320DM36x 数字视频评估模块 (DVEVM)，开发人员可直接评估 TI 的数字媒体 (DMx) 处理器，并开始构建数字视频应用，如 IP 安防摄像头、运动相机、无人机、可穿戴器件、数字标牌、可视门铃及其他数字视频产品
TMS320DM36x DVEVM 使开发人员能够编写适用于 ARM 的生产就绪型应用代码，并使用 DMx API 访问 HDVICP 协处理器核心，从而直接开始开发 TMS320DM368 和 TMS320DM365 数字媒体处理器的应用。
SLEC027 — TVP7002, TVP70025i PLL Worksheet
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HTQFP (PZP) | 100 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。