TRF372017
- Fully Integrated PLL/VCO and IQ Modulator
- LO Frequency from 300 MHz to 4.8 GHz
- 76-dBc Single-Carrier WCDMA ACPR at –8-dBm
Channel Power - OIP3 of 26 dBm
- P1dB of 11.5 dBm
- Integer/Fractional PLL
- Phase Noise –132 dBc/Hz
(at 1 MHz, fVCO of 2.3 GHz) - Low Noise Floor: –160 dBm/Hz
- Input Reference Frequency Range: Up to
160 MHz - VCO Frequency Divided by 1-2-4-8 Output
- APPLICATIONS
- Wireless Infrastructure
- CDMA: IS95, UMTS, CDMA2000,
TD-SCDMA - TDMA: GSM, IS-136, EDGE/UWC-136
- LTE
- CDMA: IS95, UMTS, CDMA2000,
- Wireless Local Loop
- Point-to-Point Wireless Access
- Wireless MAN Wideband Transceivers
- Wireless Infrastructure
All other trademarks are the property of their respective owners
TRF372017 is a high-performance, direct up-conversion device, integrating a high-linearity, low-noise IQ modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide, continuous tuning range of 300 MHz to 4800 MHz. The LO is available as an output with independent frequency dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is controlled through a 3-wire serial programming interface (SPI). A control pin invokes power-save mode to reduce power consumption while keeping the VCO locked for fast start-up.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | TRF372017 Datasheet 数据表 (Rev. E) | PDF | HTML | 2016-1-11 | ||
| 技术文章 | Can a clock generator act as a jitter cleaner? | PDF | HTML | 2017-3-23 | |||
| 技术文章 | Don’t let bad reference signals destroy the phase noise in your PLL/synthesizer | PDF | HTML | 2017-1-10 | |||
| 技术文章 | What to do when your PLL does not lock | PDF | HTML | 2016-7-12 | |||
| 技术文章 | Issues with jitter, phase noise, lock time or spurs? Check the loop-filter bandwid | PDF | HTML | 2016-6-6 | |||
| 应用手册 | Characterization Report for FMC30RF | 2014-9-18 | ||||
| 设计指南 | Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) | 2013-8-14 | ||||
| 应用手册 | Supply Noise Effect on Oscillator Phase Noise | 2011-11-22 | ||||
| 用户指南 | TSW3725 Evaluation Module | 2011-10-25 | ||||
| 应用手册 | TRF372017 Noise Analysis (Rev. A) | 2011-10-7 | ||||
| 应用手册 | LO Harmonic Effect of I/Q Modulator Sideband Suppression | 2010-5-10 | ||||
| 应用手册 | Fractional/Integer-N PLL Basics | 1998-5-13 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DAC3283EVM — DAC3283 双通道、16 位、800MSPS、1x-4x 插值数模转换器评估模块
DAC3283EVM 是能让设计者评估德州仪器 (TI) DAC3283 双通道 16 位 800MSPS 数模转换器 (DAC) 的电路板，它具有 8 字节宽 DDR LVDS 数据输入、集成 2x/4x 内插滤波器，并且在高 IF 时具有出色的线性度。EVM 提供了可在各种时钟、输入条件下测试 DAC3283 的灵活环境。作为易于使用的完整射频发射解决方案，DAC3283EVM 包含用于为 DAC3283 计时的 CDCE62005 时钟发生器/抖动消除器以及 TRF3704 50MHz 至 6GHz 正交调制器，该调制器可将来自 DAC 的 I/Q 输出向上变频为射频实信号。
该 (...)
TRF372017EVM — TRF372017 评估模块
SLWC100 — TRF372017 EVM GUI
ABACO-3P-FMC30RFFPGA — Abaco Systems® FMC30RF FPGA 夹层卡
RF-CASCADE-CALC-TOOL — TI 射频级联计算器
SLWC095 — TRF372017EVM Design Files
TIDA-00068 — 具有 DPD 反馈路径的基站收发器
该设计适用于小型蜂窝基站开发平台。其提供两条实际的接收路径、两条复杂的传输路径和一条共享的实际反馈路径。该设计具有小型蜂窝基站的尺寸，却具有大型基站的性能。当前设计可处理高达 20MHz 的带宽。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。