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线性和低压降 (LDO) 稳压器

TPS7A52

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2A、低输入电压 (1.1V)、低噪声、高精度、超低压降 (LDO) 稳压器

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TPS7A52

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产品详情

Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 45 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 45 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
VQFN-HR (RPS) 12 5.5 mm² (2.5 mm × 2.2 mm)
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 65 mV (max) at 2 A with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Power-supply ripple rejection:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 65 mV (max) at 2 A with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Power-supply ripple rejection:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package

The TPS7A52 is a low-noise (4.4 µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 2 A with only 65 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A52 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A52 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A52 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.

 

The TPS7A52 is a low-noise (4.4 µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 2 A with only 65 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A52 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A52 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A52 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.

 
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 TPS7A52 2-A, High-Accuracy (0.5%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator 数据表 (Rev. A) PDF | HTML 2020-3-23
白皮书 揭秘 LDO 开通（启动）时间 PDF | HTML PDF | HTML 2026-4-27
白皮书 使用并联 LDO 降低系统噪声 PDF | HTML 英语版 PDF | HTML 2025-11-20
白皮书 Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022-12-14
白皮书 Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022-12-13
应用手册 Point-of-Load Solutions for Network Interface Cards (NIC) PDF | HTML 2021-9-8
技术文章 Minimize noise and ripple with a low-noise buck converter PDF | HTML 2020-10-21

设计与开发

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评估板

TPS7A52EVM-031 — TPS7A52 2A 低 VIN (1.1V) 低噪声高精度超 LDO 稳压器评估模块

TPS7A52 评估模块 (EVM) 专为典型配置而设计，用于评估 TPS7A52 器件的运行情况和性能，后者是一款高精度、2A、低 VIN、低 VOUT、低压降 (LDO) 稳压器。

该 EVM 电路板被配置为适用于动态负载电流需要高达 2A 的工程应用的参考设计。

用户指南: PDF
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仿真模型

TPS7A5201RPS PSpice Model (Rev. A)

SBVM952A.ZIP (3263 KB) - PSpice 模型
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计算工具

PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator

并联低压降 (LDO) 计算器是一款基于 Microsoft® Excel® 的工具，它使用镇流电阻为并联 LDO 稳压器提供最坏情形分析。该工具可帮助用户确定所需的最低并联 LDO 稳压器数量，以及满足一组系统要求的合适镇流电阻。

计算器中预填充了并联应用中常用 LDO 稳压器的数据表信息。用户可以根据其系统要求来评估哪款 LDO 稳压器器件能够满足其系统需求。

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参考设计

TIDA-060043 — 56G 重定时器 MCB QSFP-DD 参考设计

该参考设计演示了如何使用 56G PAM-4 重定时器 DS560DF410 来均衡有源电缆应用中的高速信号。该设计是一个模块合规板 (MCB)，它通过重定时器将来自 QSFP-DD 连接器的信号按入口和出口方向路由到 SMA 和 MXP 连接器。

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封装 引脚 CAD 符号、封装和 3D 模型
VQFN-HR (RPS) 12 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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