TPS51100
- Input Voltage Range: 4.75 V to 5.25 V
- VLDOIN Voltage Range: 1.2 V to 3.6 V
- 3-A Sink/Source Termination Regulator
Includes Droop Compensation - Requires Only 20-μF Ceramic Output
Capacitance - Supports Hi-Z in S3 and Soft-Off in S5
- 1.2-V Input (VLDOIN) Helps Reduce Total
Power Dissipation - Integrated Divider Tracks 0.5 VDDQSNS for
VTT and VTTREF - Remote Sensing (VTTSNS)
- ±20-mV Accuracy for VTT and VTTREF
- 10-mA Buffered Reference (VTTREF)
- Built-In Soft-Start, UVLO, and OCL
- Thermal Shutdown
- Supports JEDEC Specifications
The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.
The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | TPS51100 3-A Sink / Source DDR Termination Regulator 数据表 (Rev. E) | PDF | HTML | 2014-12-17 | ||
| 应用手册 | LDO 噪声揭秘 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | PDF | HTML | 2020-9-16 | |
| 应用手册 | DDR VTT Power Solutions: A Competitive Analysis (Rev. A) | 2020-7-9 | ||||
| 选择指南 | 电源管理指南 2018 | 2018-7-31 | ||||
| 应用手册 | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017-8-9 | |||
| 用户指南 | Using the TPS51100 | 2004-7-13 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
TPS51116EVM-001 — TPS51116 存储器电源解决方案，同步降压控制器评估模块
The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HVSSOP (DGQ) | 10 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。