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TMS320C6412

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C64x 定点 DSP- 高达 720MHz、McBSP、McASP、I2cC、以太网

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TMS320C6412

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产品详情

CPU 32-/64-bit Frequency (MHz) 500, 600, 720 PCIe 1 PCI Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Frequency (MHz) 500, 600, 720 PCIe 1 PCI Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
OMFCBGA (GDK) 548 529 mm² (23 mm × 23 mm) OMFCBGA (ZDK) 548 529 mm² (23 mm × 23 mm) OMFCBGA (ZNZ) 548 729 mm² (27 mm × 27 mm)
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 TMS320C6412 Fixed-Point Digital Signal Processor 数据表 (Rev. J) 2010-10-12
* 勘误表 TMS320C641x、TMS320DM64x、TMS320DRA342 的 ZNZ、ZDK 封装已停产并转换 PDF | HTML PDF | HTML 2026-7-23
* 勘误表 TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J) 2010-2-4
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021-5-19
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012-8-9
应用手册 Introduction to TMS320C6000 DSP Optimization 2011-10-6
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010-7-30
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009-7-2
应用手册 TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007-9-4
应用手册 Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007-5-20
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007-4-11
产品概述 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007-4-4
用户指南 TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007-3-26
用户指南 TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) 2007-1-25
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006-12-14
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006-11-15
用户指南 TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 2006-2-28
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006-1-1
应用手册 TMS320C6412 Hardware Designer's Resource Guide (Rev. A) 2005-10-21
应用手册 Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005-10-20
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005-3-1
应用手册 TMS320C6412 Power Consumption Summary (Rev. E) 2005-1-27
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005-1-25
应用手册 Use and Handling of Semiconductor Packages With ENIG Pad Finishes 2004-8-31
用户指南 TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 2004-8-13
应用手册 TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004-4-26
应用手册 TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004-4-21
用户指南 TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 2004-3-26
用户指南 TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004-3-25
应用手册 TMS320C6000 McBSP Initialization (Rev. C) 2004-3-8
应用手册 TMS320C64x EDMA Performance Data 2004-3-5
应用手册 TMS320C6000 EDMA IO Scheduling and Performance 2004-3-5
应用手册 TMS320C64x EDMA Architecture 2004-3-3
应用手册 TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance 2003-10-31
应用手册 TMS320C64x DSP Host Port Interface (HPI) Performance 2003-10-24
用户指南 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003-7-31
用户指南 TMS320C6000 DSP Cache User's Guide (Rev. A) 2003-5-5
应用手册 Using IBIS Models for Timing Analysis (Rev. A) 2003-4-15
应用手册 TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002-6-4
应用手册 TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 2002-4-17
应用手册 TMS320C6000 Board Design for JTAG (Rev. C) 2002-4-2
应用手册 TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002-2-13
应用手册 Cache Usage in High-Performance DSP Applications with the TMS320C64x 2001-12-13
应用手册 Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001-10-31
应用手册 TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001-10-24
应用手册 Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 2001-9-30
应用手册 TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001-9-30
应用手册 Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001-8-31
应用手册 TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001-8-31
应用手册 TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001-8-31
应用手册 TMS320C6000 System Clock Circuit Example (Rev. A) 2001-8-15
应用手册 TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001-7-23
应用手册 TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001-7-10
应用手册 TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001-6-30
应用手册 TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001-6-21
应用手册 TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001-5-21
用户指南 TMS320C64x Technical Overview (Rev. B) 2001-1-30
应用手册 Circular Buffering on TMS320C6000 (Rev. A) 2000-9-12
应用手册 TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000-9-11
应用手册 TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000-2-2
应用手册 General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000-1-31
应用手册 TMS320C6000 C Compiler: C Implementation of Intrinsics 1999-12-7
应用手册 TMS320C6000 McBSP: I2S Interface 1999-9-8

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XDS560v2 是 XDS560™ 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。  请注意，它不支持串行线调试 (SWD)。

对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。  对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (...)

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TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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LB-3P-TRACE32-DSP — 适用于数字信号处理器 (DSP) 的 Lauterbach TRACE32 调试和跟踪系统

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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SPRC090 — Download TMS320C6000 Chip Support Library

芯片支持库 (CSL) 提供了一个应用程序编程接口 (API)，用于配置和控制 DSP 片上外设，以实现易用性、各种 C6000 器件间的兼容性以及硬件抽象。通过提供标准化和可移植性，可缩短开发时间。特性部分列出的功能专为以下器件而设计：C6201、C6202、C6203、C6204、C6205、C6211、C6410、C6412、C6413、C6414、C6415、C6416、C6418、C6701、C6711、C6712、C6713、DA610、DM640、DM641 和 DM642。

特性

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驱动程序或库

SPRC122 — C62x/C64x Fast Run-Time Support Library

C62x/64x FastRTS Library 是优化型浮点函数库，适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用，最佳执行速度是这些应用的关键。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library，可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数单精度和双精度转换函数
浮点加法将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
支持的产品和硬件
驱动程序或库

SPRC264 — TMS320C5000/6000 图像库 (IMGLIB)

C5000/6000 图像处理库 (IMGLIB) 是一款经过优化的图像/视频处理函数库，适用于 C 语言程序员。其中包括计算量庞大的实时应用程序常用的可使用 C 语言调用的通用影像/视频处理例程。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，IMGLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 数字信号处理器库 (DSPLIB) 是一款平台优化型 DSP 函数库，适用于 C 编程器。它包括 C 语言可调用的通用信号处理例程，通常用于计算密集型的实时应用中。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，DSPLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件
软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司，提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息，请访问 https://www.adaptivedigital.com。
来源：Adaptive Digital Technologies, Inc.
支持的产品和硬件
仿真模型

C6412 GDK BSDL Model

SPRM123.ZIP (9 KB) - BSDL 模型
支持的产品和硬件
仿真模型

C6412 GDK/GNZ IBIS Model

SPRM110.ZIP (109 KB) - IBIS 模型
支持的产品和硬件
仿真模型

C6412 GNZ BSDL Model

SPRM122.ZIP (9 KB) - BSDL 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
OMFCBGA (GDK) 548 Ultra Librarian
OMFCBGA (ZDK) 548 Ultra Librarian
OMFCBGA (ZNZ) 548 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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