SN65LVELT22
- 450 ps (typ) Propagation Delay
- Operating Range: VCC 3.0 V to 3.8 with
GND = 0 V - <50 ps (max) Output to Output Skew
- Built-in Temperature Compensation
- Drop in Compatible to MC100LVELT22
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.
The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 3.3 V Dual LVTTL to Differential LVPECL Translator 数据表 | 2008-12-12 | |||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007-10-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
订购和质量
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