SN65ELT23
- Dual 5-V Differential PECL-to-TTL Buffer
- 24-mA TTL Ouputs
- Operating Range
- PECL VCC = 4.75 V to 5.25 V with GND = 0 V
- Support for Clock Frequencies of 250 MHz (TYP)
- 3.5-ns Typical Propagation Delay
- Output Default Low with Inputs Left Open or <1.3 V
- Internal Input 50-k
Pull-Down Resistor - Built-In Temperature Compensation
- Drop-In Compatible to the MC100ELT23
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
技术文档
未找到结果。请清除搜索并重试。
查看全部 2
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 5-V Dual Differential PECL Buffer-to-TTL Translator 数据表 | 2009-6-30 | |||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007-10-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |