LMH0356
- Supports SMPTE ST-424, ST-292, and ST-259
Serial Digital Video Standards - Supports 270-Mbps, 1.483-Gbps, 1.485-Gbps,
2.967-Gbps, and 2.97-Gbps Serial Data Rate
Operation - Supports DVB-ASI at 270 Mbps
- Single 3.3-V Supply Operation
- 430-mW Typical Power Consumption
- Integrated 4:1 Multiplexed Input
- 0 to 30-inch FR4 Equalizer on Each Multiplexed
Input - Two Differential, Reclocked Outputs
- Choice of Second Reclocked Output or
Recovered Clock Output - Single 27-MHz External Crystal or Reference
Clock Input - Manual Rate Select Input
- SD/HD Operating Rate Indicator Output
- Lock Detect Indicator Output
- Output Mute Function for Data and Clock
- Auto/Manual Reclocker Bypass
- Power Saver Mode With Device Power-Down
Control (10-mW Typical Power Consumption in
Disabled State) - Differential LVPECL-Compatible Serial
Data Inputs and Outputs - LVCMOS Control Inputs and Indicator Outputs
- 48-Pin WQFN or 40-Pin WQFN Package
- Industrial Temperature Range: –40°C to 85°C
- 48-Pin WQFN Version Footprint-Compatible with
the LMH0056 and LMH0036
The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs retimes serial digital video data conforming to the SMPTE ST-424, ST-292, and ST-259 standards. The LMH0356 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0356 supports DVB-ASI operation at 270 Mbps. The LMH0356 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. In addition, the four inputs of the LMH0356 each have an FR4 equalizer capable of equalizing 0 to 30 inches of FR4 trace length.
The LMH0356 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0356 recovers the serial data-rate clock and optionally provides it as an output. The LMH0356 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass, output mute, and device enable. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100-Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.
The LMH0356 is powered from a single 3.3-V supply. Power dissipation is typically 430 mW. The device is available in two space-saving packages: a 7-mm × 7-mm, 48-pin WQFN and even more space-efficient 5-mm × 5-mm, 40-pin WQFN package.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs 数据表 (Rev. L) | PDF | HTML | 2016-1-12 | ||
| 选择指南 | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | 2017-4-5 | |||
| 应用手册 | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013-4-26 | ||||
| 应用手册 | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1983 LMH0356 Customization with SMBus (Rev. A) | 2013-4-26 | ||||
| 用户指南 | 3 Gbps HD SD SDI Reclocker with 4:1 Input Mux and FR4 EQs Eval Bd User Guide | 2012-1-26 | ||||
| 应用手册 | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009-11-12 | ||||
| 应用手册 | Reference Clock Loop Through Application | 2009-1-16 | ||||
| 应用手册 | Design Considerations for SMPTE 3 Gbps SDI Interfaces | 2009-1-15 | ||||
| 应用手册 | 3G-SDI: 32 Loop Cascade Analysis | 2008-10-23 | ||||
| 应用手册 | DS25CP104 in 3G SDI Router Application | 2008-8-20 | ||||
| 设计指南 | Broadcast Video Owner's Manual | 2006-11-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
| WQFN (RSB) | 40 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。