LMH0346
- Supports SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) Serial Digital Video Standards
- Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps Serial Data Rate Operation
- Supports DVB-ASI at 270 Mbps
- Single 3.3V Supply Operation
- 370 mW Typical Power Consumption
- Two Differential, Reclocked Outputs
- Choice of Second Reclocked Output or Low-Jitter, Differential, Data-Rate Clock Output
- Single 27 MHz External Crystal or Reference Clock Input
- Manual or Automatic Rate Select Input
- SD/HD Operating Rate Indicator Output
- Lock Detect Indicator Output
- Output Mute Function for Data and Clock
- Auto/Manual Reclocker Bypass
- Differential LVPECL Compatible Serial Data Inputs and Outputs
- LVCMOS Control Inputs and Indicator Outputs
- 20-Pin HTSSOP or 24-Pin WQFN Package
- Industrial Temperature Range: -40°C to +85°C
- Footprint Compatible With the LMH0046 and LMH0026 (HTSSOP Package)
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The LMH0346 3 Gbps HD/SD SDI Reclocker retimes serial digital video data conforming to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) standards. The LMH0346 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0346 supports DVB-ASI operation at 270 Mbps.
The LMH0346 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0346 recovers the serial data-rate clock and optionally provides it as an output. The LMH0346 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.
The LMH0346 is powered from a single 3.3V supply. Power dissipation is typically 370 mW.
The device is available in two space-saving packages: a 6.5 X 4.4 mm 20-pin HTSSOP and an even more space–efficient 5 X 4 mm 24-pin WQFN package.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMH0346 3 Gbps HD/SD SDI Reclocker with Dual Differential Outputs 数据表 (Rev. J) | 2013-4-15 | |||
| 选择指南 | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | 2017-4-5 | |||
| 应用手册 | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013-4-26 | ||||
| 应用手册 | AN-1977 LMH0346 Customization with SMBus (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-2004 Replacing the CLC016 Reclocker with the LMH0026 (Rev. A) | 2013-4-26 | ||||
| 用户指南 | SD3GDAEVK User Guide | 2013-4-5 | ||||
| 应用手册 | TI SDI 传输方案 | 2012-10-25 | ||||
| 用户指南 | 3 Gbps HD SD SDI Reclocker with Dual Differential Outputs Eval Bd User Guide | 2012-1-26 | ||||
| 应用手册 | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009-11-12 | ||||
| 应用手册 | Reference Clock Loop Through Application | 2009-1-16 | ||||
| 设计指南 | Broadcast Video Owner's Manual | 2006-11-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (NHZ) | 24 | Ultra Librarian |
| HTSSOP (PWP) | 20 | Ultra Librarian |
订购和质量
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