LMH0071
- 5-Bit LVDS Interface
- No External VCO or Clock Required
- Reclocked Serial Loopthrough With Cable Driver
- Powerdown Mode
- 3.3V SMBus Configuration Interface
- Small 48-Pin WQFN Package
- Industrial Temperature range: -40°C to +85°C
Key Specifications
- Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
- Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
- 0.6 UI Minimum Input Jitter Tolerance
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.
The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F 数据表 (Rev. Q) | 2013-4-16 | |||
| 选择指南 | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | 2017-4-5 | |||
| 应用手册 | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013-4-26 | ||||
| 应用手册 | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | 2013-4-26 | ||||
| 应用手册 | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009-11-12 | ||||
| 应用手册 | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | 2008-3-18 | ||||
| 设计指南 | Broadcast Video Owner's Manual | 2006-11-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
SDXILIP — Xilinx Spartan 示例代码
We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |