LMH0040
- LVDS Interface to Host FPGA
- No External VCO or Clock Ref Required
- Integrated Variable Output Cable Driver
- 3.3V SMBus Configuration Interface
- Integrated TXCLK PLL Cleans Clock Noise
- Small 48-Pin WQFN Package
- Industrial Temperature range: -40°C to 85°C
Key Specifications
- Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
- Typical Power Dissipation: 440 mW
- 30 ps Typical Output Jitter (HD, 3G)
All trademarks are the property of their respective owners.
The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.
The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.
The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMH0340/040/070/050 3Gbps, HD, SD, DVB-ASI SDI Serializr & Cable Drvr w/LVDS I/F 数据表 (Rev. I) | 2013-4-16 | |||
| 应用手册 | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013-4-26 | ||||
| 应用手册 | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013-4-26 | ||||
| 应用手册 | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | 2013-4-26 | ||||
| 应用手册 | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009-11-12 | ||||
| 应用手册 | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | 2008-3-18 | ||||
| 设计指南 | Broadcast Video Owner's Manual | 2006-11-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
SDXILIP — Xilinx Spartan 示例代码
We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |