DS91D176
- DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
- Optimal for ATCA, uTCA Clock Distribution Networks
- Meets or Exceeds TIA/EIA-899 M-LVDS Standard
- Wide Input Common Mode Voltage for Increased Noise Immunity
- DS91D176 has Type 1 Receiver Input
- DS91C176 has Type 2 Receiver with Fail-safe
- Industrial Temperature Range
- Space Saving SOIC-8 Package
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The DS91C176 and DS91D176 are 100 MHz single channel M-LVDS (Multipoint Low Voltage Differential Signaling) transceivers designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancements that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.
The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signals. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 has an M-LVDS type 2 receiver which enable failsafe functionality.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers 数据表 (Rev. L) | 2013-4-16 | |||
| 应用简报 | How Far, How Fast Can You Operate MLVDS? | 2018-8-6 | ||||
| 应用手册 | Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) | 2013-4-26 | ||||
| 应用手册 | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013-1-3 | ||||
| 应用手册 | Designing an ATCA Compliant M-LVDS Clock Distribution Network (cn) | 2007-11-20 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
订购和质量
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