DS90LV031A
- >400-Mbps (200-MHz) Switching Rates
- 0.1-ns Typical Differential Skew
- 0.4-ns Maximum Differential Skew
- 2-ns Maximum Propagation Delay
- 3.3-V Power Supply Design
- ±350-mV Differential Signaling
- Low Power Dissipation (13-mW at 3.3-V Static)
- Interoperable With Existing 5-V LVDS Devices
- Compatible With IEEE 1596.3 SCI LVDS Standard
- Compatible With TIA/EIA-644 LVDS Standard
- Industrial Operating Temperature Range
- Available in SOIC and TSSOP Surface-Mount Packaging
The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.
The DS90LV031A accepts low voltage LVTTL or LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE® function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical.
The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90LV031A 3-V LVDS Quad CMOS Differential Line Driver 数据表 (Rev. D) | PDF | HTML | 2016-8-25 | ||
| 应用手册 | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004-5-15 | ||||
| 应用手册 | An Overview of LVDS Technology | 1998-10-5 |
设计与开发
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DS90LV047-48AEVM — DS90LV047-48AEVM 评估模块
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
订购和质量
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