DS90C032QML
- Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
- High Impedance LVDS Inputs with Power-Off.
- Accepts Small Swing (330 mV) Differential Signal Levels
- Low Power Dissipation
- Low Differential Skew
- Low Chip to Chip Skew
- Pin Compatible with DS26C32A
- Compatible with IEEE 1596.3 SCI LVDS Standard
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The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90C032QML LVDS Quad CMOS Differential Line Receiver 数据表 (Rev. D) | 2013-4-12 | |||
| * | 辐射与可靠性报告 | DS90C032xLQMLV SEE Report | 2012-5-9 | |||
| * | 辐射与可靠性报告 | DS90C032xLQMLV TID Report | 2012-5-9 | |||
| * | SMD | DS90C032QML SMD 5962-95834 | 2016-6-21 | |||
| 应用简报 | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018-8-3 | ||||
| 应用简报 | How to Terminate LVDS Connections with DC and AC Coupling | 2018-5-16 | ||||
| 应用手册 | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004-5-15 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| LCCC (NAJ) | 20 | Ultra Librarian |
订购和质量
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