DS25CP114
- DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
- Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture
- Pin (Two Levels) and SMBus (Four Levels) Selectable Pre-Emphasis and Equalization Eliminate ISI Jitter
- Wide Input Common Mode Range Enables Easy Interface to CML and LVPECL Drivers
- LOS Circuitry Detects Open Inputs Fault Condition
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space The DS25CP114 Eliminates the On-Chip Input Termination for Added Design Flexibility.
- 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 6 mm x 6 mm WQFN-40 Space Saving Package
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS25CP104A/CP114 3.125 Gbps 4x4 LVDS Xpoint Sw w/Xmit Pre-Emp & Receive Equal 数据表 (Rev. C) | 2013-3-4 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |
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