DP83843
- IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
and built-in filters - IEEE 802.3u 100BASE-TX compatible - directly drives
standard Category 5 UTP, no need for external
100BASE-TX transceiver - Fully Integrated and fully compliant ANSI X3.263 TPPMD
physical sublayer which includes adaptive equalization
and BLW compensation - IEEE 802.3u 100BASE-FX compatible - connects directly
to industry standard Electrical/Optical transceivers - IEEE 802.3u Auto-Negotiation for automatic speed selection
- IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface - Integrated high performance 100 Mb/s clock recovery
circuitry requiring no external filters - Full Duplex support for 10 and 100 Mb/s data rates
- MII Serial 10 Mb/s mode
- Fully configurable node/switch and 100Mb/s repeater
modes - Programmable loopback modes for flexible systemdiagnostics
- Flexible LED support
- Single register access to complete PHY status
- MDIO interrupt support
- Individualized scrambler seed for 100BASE-TX applications
using multiple PHYs - Low power consumption for multi-port applications
- Small footprint 80-pin PQFP package
The DP83843BVJE is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols.
This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber media via industry standard electrical/optical fiber PMD transceivers. This device also interfaces directly to the MAC layer through the IEEE 802.3u standard Media Independent Interface (MII), ensuring interoperability between products from different vendors.
The DP83843 is designed with National Semiconductor’s advanced CMOS process. Its system architecture is based on the integration of several of National's industry proven core technologies:
- IEEE 802.3 ENDEC with AUI/10BASE-T transceiver module to provide the 10 Mb/s functions
- Clock Recovery/Generator Modules fromNational's Fast Ethernet and FDDI products
- FDDI Stream Cipher scrambler/descrambler for TP-PMD
- 100BASE-Xphysical codingsub-layer (PCS) andcontrol logic that integrates the core modules into a dual speed Ethernet physical layer controller
- ANSI X3T12 Compliant TP-PMD Transceiver technology with Baseline Wander (BLW) compensation
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DP83843 PHYTER 数据表 (Rev. B) | 2013-11-13 | |||
| 应用手册 | How to Pass IEEE Ethernet Compliance Tests | PDF | HTML | 2021-9-20 | |||
| 应用手册 | AN-1506 DP83843 to DP83848C/I/YB PHYTER System Rollover Document (Rev. A) | 2013-4-26 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
ETHERNET-SW — 以太网 PHY 驱动程序和工具
德州仪器 (TI) 以太网物理层 (PHY) 收发器的驱动程序支持通过串行管理接口 (MDC/MDIO) 进行通信，从而配置和读取 PHY 寄存器。Linux 和 RTOS 驱动程序可在我们的 GitHub 上找到。
USB-2-MDIO — USB-2-MDIO Tool v1.0
借助 USB-2-MDIO 软件工具，德州仪器 (TI) 的以太网 PHY 可访问 MDIO 状态和器件控制寄存器。 USB-2-MDIO 工具包括一个 LaunchPad™ 开发套件，适用于与轻量级 GUI 连接的 TI MSP430™ MCU。 此 LaunchPad 开发套件实现了一个 MDIO 总线控制器，该控制器可以操作连接到总线的 PHY 上的寄存器。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| QFP (NNC) | 80 | Ultra Librarian |