CDCLVP2106

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低抖动双路 1:6 通用至 LVPECL 缓冲器

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数据表

document-pdfAcrobat CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. B) (英语) PDF | HTML

CDCLVP2106

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产品详情

Number of outputs

12

Additive RMS jitter (typ) (fs)

124

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

124

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Dual 1:6 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 92 mA
Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Within Bank Output Skew: 20 ps
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C
to +85°C
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 6-mm × 6-mm, 40-Pin VQFN
(RHA) Package
ESD Protection Exceeds 2000 V (HBM)

Dual 1:6 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 92 mA
Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Within Bank Output Skew: 20 ps
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C
to +85°C
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 6-mm × 6-mm, 40-Pin VQFN
(RHA) Package
ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. B)	PDF \| HTML			2013-10-25

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评估板

CDCLVP2106EVM — CDCLVP2106 评估模块

CDCLVP2106 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器，支持单端或差动时钟输入。每个输入可馈给 6 个 LVPECL 输出。该器件还具有片上偏压发生器，它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP2106 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP2106 的所有功能进行全面验证。为达到最佳性能，该评估板配备有 50Ω SMA 连接器和受控良好的 50Ω 阻抗微带传输线。

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