主页 时钟和计时 时钟缓冲器
主页
时钟和计时
时钟缓冲器

CDCLVP2104

正在供货

低抖动双路 1:4 通用至 LVPECL 缓冲器

立即订购
数据表

CDCLVP2104

正在供货
数据表 立即订购

产品详情

Number of outputs 8 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Number of outputs 8 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² (5 mm × 5 mm)
  • Dual 1:4 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 78 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum 15 ps Within Bank Output Skew
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
  • ESD Protection Exceeds 2000 V (HBM)
  • Dual 1:4 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 78 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum 15 ps Within Bank Output Skew
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
  • ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.
filter 查找其他 时钟缓冲器
下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相似。
LMK1D2104 正在供货 双组 4 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器 Same pinout with wider supported voltage range and LVPECL vs LVDS
LMK00301 正在供货 3-GHz 10 路输出差动扇出缓冲器/电平转换器 1:10 universal differential buffer that can support LVPECL

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. B) PDF | HTML 2013-10-25
用户指南 CDCLVP2104 User's Guide 2009-10-21

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

CDCLVP2104EVM — CDCLVP2104 评估模块

CDCLVP2104 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器，支持单端或差动时钟输入。每个输入可馈给 4 个 LVPECL 输出。该器件还具有片上偏压发生器，它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP2104 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP2104 器件的所有功能进行全面验证。为达到最佳性能，该评估板配备有 50Ω SMA 连接器和受控良好的 50Ω 阻抗微带传输线。
支持的产品和硬件
有库存
限制：
??asset.out-of-stock-ti_zh_CN??
无货
仿真模型

CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS 模型
支持的产品和硬件
设计工具

CLOCK-TREE-ARCHITECT — 时钟树架构编程软件

时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。

支持的产品和硬件
设计工具

PLLATINUMSIM-SW — PLL 环路滤波器、相位噪声、锁定时间和杂散模拟工具

PLLATINUMSIM-SW 是一款仿真工具，允许用户创建我们 PLLatinum™ 集成电路的详细设计和仿真，其中包括 LMX 系列锁相环 (PLL) 和合成器。

支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RHD) 28 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频