CDCLVP1212
- 2:12 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL - 12 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 88 mA
- Very Low Additive Jitter: <100 fs, rms in 10-kHz to
20-MHz Offset Range:- 57 fs, rms (typ) @ 122.88 MHz
- 48 fs, rms (typ) @ 156.25 MHz
- 30 fs, rms (typ) @ 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Output Skew: 25 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to 85°C
- ESD Protection Exceeds 2 kV (HBM)
- Supports 105°C PCB Temperature (Measured
with a Thermal Pad) - Available in 6-mm × 6-mm QFN-40 (RHA) Package
The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from –40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CDCLVP1212 LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. E) | PDF | HTML | 2015-12-2 | ||
| 应用手册 | Clocking Design Guidelines: Unused Pins | 2015-11-19 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
PLLATINUMSIM-SW — PLL 环路滤波器、相位噪声、锁定时间和杂散模拟工具
PLLATINUMSIM-SW 是一款仿真工具，允许用户创建我们 PLLatinum™ 集成电路的详细设计和仿真，其中包括 LMX 系列锁相环 (PLL) 和合成器。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RHA) | 40 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。