CDCLVD2106

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低抖动双路 1:6 通用至 LVDS 缓冲器

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数据表

document-pdfAcrobat Dual 1:6 Low Additive Jitter LVDS Buffer 数据表 (Rev. B) (英语)

CDCLVD2106

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产品详情

Number of outputs

12

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Dual 1:6 Differential Buffer
Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
Low Within Bank Output Skew of 45 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Six Outputs
Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

Dual 1:6 Differential Buffer
Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
Low Within Bank Output Skew of 45 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Six Outputs
Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	Dual 1:6 Low Additive Jitter LVDS Buffer 数据表 (Rev. B)				2011-1-17

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评估板

CDCLVD2106EVM — CDCLVD2106 评估模块

CDCLVD1212/CDCLVD2106 是高性能、低附加抖动时钟缓冲器。它们具有两个通用输入缓冲器，支持单端或差动时钟输入，可通过控制引脚（仅限 CDCLVD1212）进行选择。这两种器件还具有片上偏压发生器，该发生器可以为器件输入提供 LVDS 共模电压。评估模块 (EVM) 旨在演示 CDCLVD1212 或 CDCLVD2106 的电性能。然而，那些对 CDCLVD1216 或 CDCLVD2108 感兴趣的客户也可以使用此 EVM。这个完全组装且经过工厂测试的评估板允许对器件的所有功能进行全面验证。为达到最佳性能，该评估板配备有 SMA 连接器和受控良好的 50Ω 阻抗微带传输线。

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