CDCE62005
- Superior Performance:
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz - Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
- Flexible Frequency Planning:
- 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
- Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
- Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
- Output Frequency up to 1.5 GHz in Fan-Out Mode
- Independent Coarse Skew Control on all Outputs
- High Flexibility:
- Integrated EEPROM Determines Device Configuration at Power-up
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
- 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
- –40°C to +85°C Temperature Range
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).
The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs 数据表 (Rev. G) | PDF | HTML | 2016-5-23 | ||
| 用户指南 | TSW6011EVM Quick Start Guide (Rev. D) | 2016-8-17 | ||||
| 应用手册 | Clocking Design Guidelines: Unused Pins | 2015-11-19 | ||||
| 应用手册 | Effects of Clock Spur on High Speed DAC Performance (Rev. A) | 2015-5-18 | ||||
| 应用手册 | Effects of Clock Noise on High Speed DAC Performance | 2012-11-8 | ||||
| 应用手册 | Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 | 2011-8-11 | ||||
| 应用手册 | CDCE62005 锁相环电路设计与应用 | 2010-2-23 | ||||
| 应用手册 | CDCE62005 Application Report | 2008-11-21 | ||||
| 应用手册 | LAN & WAN clock generation and muxing using the CDCE62005 | 2008-11-19 | ||||
| 用户指南 | Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz | 2008-11-11 | ||||
| 应用手册 | CDCE62005 Phase Noise and Jitter Cleaning Performance | 2008-9-5 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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