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CDC208

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5V 双路 1:4 时钟驱动器

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数据表

CDC208

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数据表 立即订购

产品详情

Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 1000 Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 1000 Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm)
  • Low-Skew Propagation Delay Specifications for Clock-Driver Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Flow-Through Architecture Optimizes
    PCB Layout
  • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-um Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (DW)

EPIC is a trademark of Texas Instruments Incorporated.
  • Low-Skew Propagation Delay Specifications for Clock-Driver Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Flow-Through Architecture Optimizes
    PCB Layout
  • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-um Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (DW)

EPIC is a trademark of Texas Instruments Incorporated.

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Dual 1-Line To 4-Line Clock Drivers With 3-State Outputs 数据表 (Rev. F) 1998-10-28

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