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参数

Output options Adjustable Output, Fixed Output, Dual Output Iout (Max) (A) 0.25 Vin (Max) (V) 6 Vin (Min) (V) 2.7 Vout (Max) (V) 5.5 Vout (Min) (V) 1.2 Fixed output options (V) 1.2, 1.5, 1.8, 3.3 Noise (uVrms) 65 Iq (Typ) (mA) 0.19 Thermal resistance θJA (°C/W) 32 Load capacitance (Min) (µF) 10 Rating Catalog Regulated outputs (#) 2 Features Enable, Output Discharge, Power Good Accuracy (%) 2 PSRR @ 100 KHz (dB) 20 Dropout voltage (Vdo) (Typ) (mV) 83 Operating temperature range (C) -40 to 125 open-in-new 查找其它 线性稳压器(LDO)

封装|引脚|尺寸

HTSSOP (PWP) 20 42 mm² 6.5 x 6.4 open-in-new 查找其它 线性稳压器(LDO)

特性

  • Dual Output Voltages for Split-Supply Applications
  • Independent Enable Functions (See Part Number TPS707xx for Sequenced Outputs)
  • Output Current Range of 250 mA on Regulator 1 and 125 mA on Regulator 2
  • Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs
  • Open Drain Power-On Reset with 120-ms Delay
  • Open Drain Power Good for Regulator 1 and Regulator 2
  • Ultralow 190-µA (typ) Quiescent Current
  • 1-µA Input Current During Standby
  • Low Noise: 65 µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • One Manual Reset Input
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD Is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

open-in-new 查找其它 线性稳压器(LDO)

描述

The TPS708xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 250 mA and 125 mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution.

The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at TJ = +25°C.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high impedance state after a 120-ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR.

The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.

open-in-new 查找其它 线性稳压器(LDO)
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技术文档

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类型 标题 下载最新的英文版本 发布
* 数据表 Dual-Output Low-Dropout Voltage Regulators 数据表 2007年 12月 20日
技术文章 LDO basics: capacitor vs. capacitance 2018年 8月 1日
技术文章 LDO Basics: Preventing reverse current 2018年 7月 25日
技术文章 LDO basics: introduction to quiescent current 2018年 6月 20日
应用手册 LDO Noise Demystified 2017年 8月 9日
应用手册 LDO PSRR Measurement Simplified 2017年 8月 9日
技术文章 LDO basics: noise – part 1 2017年 6月 14日
应用手册 简化的 LDO PSRR 测量 下载最新的英文版本 (Rev.A) 2010年 7月 28日
应用手册 Power Supply Sequencing Solutions for Dual Supply Voltage DSPs 2000年 7月 5日

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