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TPS657120

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TPS657120

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产品详情

Processor supplier NVIDIA Processor name Tegra Regulated outputs (#) 5 Step-down DC/DC converter 3 Step-up DC/DC converter 0 LDO 2 Vin (min) (V) 2 Vin (max) (V) 5.5 Vout (min) (V) 0.8 Vout (max) (V) 3.6 Iout (max) (A) 2.5 Configurability Factory programmable, Software configurable Features Power good, Power sequencing Rating Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.06 Switching frequency (max) (kHz) 2600 Shutdown current (ISD) (typ) (µA) 55 Switching frequency (typ) (kHz) 2400
Processor supplier NVIDIA Processor name Tegra Regulated outputs (#) 5 Step-down DC/DC converter 3 Step-up DC/DC converter 0 LDO 2 Vin (min) (V) 2 Vin (max) (V) 5.5 Vout (min) (V) 0.8 Vout (max) (V) 3.6 Iout (max) (A) 2.5 Configurability Factory programmable, Software configurable Features Power good, Power sequencing Rating Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.06 Switching frequency (max) (kHz) 2600 Shutdown current (ISD) (typ) (µA) 55 Switching frequency (typ) (kHz) 2400
DSBGA (YFF) 30 5.71999999999999912 mm² (— mm × — mm)
  • 3 Step-Down Converters:
    • VIN Range From 2.8 V to 5.5 V
    • Power Save Mode at Light Load Current
    • Output Voltage Accuracy in PWM Mode ±2%
    • Typical 16-µA Quiescent Current per DCDC1
      and DCDC2 Converter
    • Typical 26-µA Quiescent Current for DCDC3
      Converter
    • Dynamic Voltage Scaling
    • 100% Duty Cycle for Lowest Dropout
  • 2 LDOs:
    • 2 × 10-mA Output Current
    • Low Noise RF-LDOs
    • Output Voltage Range 1.2 V to 3.4 V
    • 32-µA Quiescent Current
    • Pre-Regulation Support by Separate Power
      Inputs
    • ECO mode
    • VIN Range of LDOs:
      • LDO1: 2.0 V to 5.5 V
      • LDO2: 2.8 V to 5.5 V
  • 2 GPIOs
  • Thermal Shutdown
  • Bypass Switch
    • Used with DCDC3 Powering an RF-PA
  • Interface
    • 26 MHz-MIPI RFFE Interface
  • Undervoltage Lockout
  • Flexible Power-Up and Power-Down Sequencing
  • 2.5-mm × 2.3-mm DSBGA Package with 0.4-mm
    Pitch
  • 3 Step-Down Converters:
    • VIN Range From 2.8 V to 5.5 V
    • Power Save Mode at Light Load Current
    • Output Voltage Accuracy in PWM Mode ±2%
    • Typical 16-µA Quiescent Current per DCDC1
      and DCDC2 Converter
    • Typical 26-µA Quiescent Current for DCDC3
      Converter
    • Dynamic Voltage Scaling
    • 100% Duty Cycle for Lowest Dropout
  • 2 LDOs:
    • 2 × 10-mA Output Current
    • Low Noise RF-LDOs
    • Output Voltage Range 1.2 V to 3.4 V
    • 32-µA Quiescent Current
    • Pre-Regulation Support by Separate Power
      Inputs
    • ECO mode
    • VIN Range of LDOs:
      • LDO1: 2.0 V to 5.5 V
      • LDO2: 2.8 V to 5.5 V
  • 2 GPIOs
  • Thermal Shutdown
  • Bypass Switch
    • Used with DCDC3 Powering an RF-PA
  • Interface
    • 26 MHz-MIPI RFFE Interface
  • Undervoltage Lockout
  • Flexible Power-Up and Power-Down Sequencing
  • 2.5-mm × 2.3-mm DSBGA Package with 0.4-mm
    Pitch

The TPS657120 provides three configurable step-down converters with up to 2-A output current.This device also has 2 LDO regulators. LDO1 can be supplied from either the input voltage directly or from a pre-regulated supply such as DCDC1 or DCDC2. The input voltage to LDO2 is used as an analog supply input and therefore must be tied to the input voltage at the same voltage level with VINDCDC1/2 and VINDCDC3. The internal power-up and power-down controller is configurable and can support any power-up/power-down sequences (OTP based). All LDOs and DCDC converters are controllable by a MIPI RFFE compatible interface, by pins PWRON, CLK_REQ1 and CLK_REQ2, or both. In addition, there is a nRESET as well as a RFFE address select (ADR_SELECT) input which can alternatively be used as general purpose I/Os with a 1-mA sink capability. The TPS657120 comes in a 6-ball × 5-ball DSBGA package (2.5 mm × 2.3 mm) with a 0.4-mm pitch.

The TPS657120 provides three configurable step-down converters with up to 2-A output current.This device also has 2 LDO regulators. LDO1 can be supplied from either the input voltage directly or from a pre-regulated supply such as DCDC1 or DCDC2. The input voltage to LDO2 is used as an analog supply input and therefore must be tied to the input voltage at the same voltage level with VINDCDC1/2 and VINDCDC3. The internal power-up and power-down controller is configurable and can support any power-up/power-down sequences (OTP based). All LDOs and DCDC converters are controllable by a MIPI RFFE compatible interface, by pins PWRON, CLK_REQ1 and CLK_REQ2, or both. In addition, there is a nRESET as well as a RFFE address select (ADR_SELECT) input which can alternatively be used as general purpose I/Os with a 1-mA sink capability. The TPS657120 comes in a 6-ball × 5-ball DSBGA package (2.5 mm × 2.3 mm) with a 0.4-mm pitch.
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* 数据表 TPS657120 PMU for Baseband and RF-PA Power 数据表 (Rev. A) PDF | HTML 2015-12-31

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封装 引脚 CAD 符号、封装和 3D 模型
DSBGA (YFF) 30 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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