TPS59116
- Synchronous Buck Controller (VDDQ)
- Wide-Input Voltage Range: 3.0-V to 28-V
- D-CAP™ Mode with 100-ns Load Step Response
- Current Mode Option Supports Ceramic Output Capacitors
- Supports Soft-Off in S4/S5 States
- Current Sensing from RDS(on) or Resistor
- 2.5-V (DDR), 1.8-V (DDR2), Adjustable to 1.5-V (DDR3) or
Output Range 0.75-V to 3.0-V - Equipped with Powergood, Overvoltage Protection and
Undervoltage Protection
- 3-A LDO (VTT), Buffered Reference (VREF)
- Capable to Sink and Source 3 A
- LDO Input Available to Optimize Power Losses
- Requires Small 20-µF Ceramic Output Capacitor
- Buffered Low Noise 10-mA VREF Output
- Accuracy ±20 mV for both VREF and VTT
- Supports High-Z in S3 and Soft-Off in S4/S5
- Thermal Shutdown
- APPLICATIONS
- DDR/DDR2/DDR3/LPDDR3 Memory Power
Supplies in Embedded Computing System - SSTL-2 SSTL-18 and HSTL Termination
- DDR/DDR2/DDR3/LPDDR3 Memory Power
D-CAP, PowerPAD are trademarks of Texas Instruments.
The TPS59116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, and DDR3 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The TPS59116 offers the lowest total solution cost in systems where space is at a premium. The TPS59116 synchronous controller runs fixed 400-kHz pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The TPS59116 supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). TPS59116 has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4×4 QFN.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | Complete DDR, DDR2 and DDR3 Memory Power Solution SBC 数据表 | 2010年 4月 30日 | |||
选择指南 | 电源管理指南 2018 (Rev. K) | 2018年 7月 31日 | ||||
选择指南 | 电源管理指南 2018 (Rev. R) | 2018年 6月 25日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
封装 | 引脚 | 下载 |
---|---|---|
VQFN (RGE) | 24 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
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