SN74LVC1G79
- Available in the Texas Instruments NanoFree™ package
- Latch-up performance exceeds 100mA per JESD 78, Class II
- Supports 5V VCC operation
- Inputs accept voltages to 5.5V
- Supports down translation to VCC
- Maximum tpd of 6ns at 3.3V and 50pF load
- Low power consumption, 10µA maximum ICC
- ±24mA output drive at 3.3V
- Ioff supports partial-power-down mode and back-drive protection
The SN74LVC1G79 device is a single positive-edge-triggered D-type flip-flop that is designed for 1.65V to 5.5V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN74LVC1G79 Single Positive-Edge-Triggered D-Type Flip-Flop 数据表 (Rev. V) | PDF | HTML | 2026-8-13 | ||
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 |
设计与开发
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5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑评估模块
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
| SOT-5X3 (DRL) | 5 | Ultra Librarian |
| DSBGA (YZP) | 5 | Ultra Librarian |