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产品详情

Number of channels 2 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 2 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SSOP (DB) 16 48.36 mm² (6.2 mm × 7.8 mm) VQFN (RGY) 16 14 mm² (4 mm × 3.5 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) TVSOP (DGV) 16 23.04 mm² (3.6 mm × 6.4 mm)
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs 数据表 (Rev. Q) PDF | HTML 2015-8-31
选择指南 Logic Guide (Rev. AC) PDF | HTML 2025-11-13
产品概述 使用离散逻辑的可配置定时复位 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2023-5-15
应用手册 具有响应检测和系统复位功能的控制器 PDF | HTML 英语版 PDF | HTML 2023-3-22
应用手册 使用 SN74LVC1G123 单稳多谐振荡器进行设计 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2021-7-20

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仿真模型

HSPICE Model for SN74LV123A

SCLJ019.ZIP (111 KB) - HSpice 模型
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仿真模型

SN74LV123A IBIS Model (Rev. A)

SCEM125 (16 KB) - IBIS 模型
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仿真模型

SN74LV123A PSpice Model (Rev. C)

SCEM569C.ZIP (384 KB) - PSpice 模型
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封装 引脚 CAD 符号、封装和 3D 模型
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian
VQFN (RGY) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian

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