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单稳多谐振荡器（单稳态）

SN74LV123A

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双路可重触发单稳态多谐振荡器

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SN74LV123A

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产品详情

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
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类型 项目标题 下载最新的英语版本 日期
* 数据表 SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs 数据表 (Rev. Q) PDF | HTML 2015年 8月 31日
更多文献资料 使用离散逻辑的可配置定时复位 (Rev. A) PDF | HTML 下载英文版本 (Rev.A) PDF | HTML 2023年 5月 15日
应用手册 具有响应检测和系统复位功能的控制器 PDF | HTML 下载英文版本 PDF | HTML 2023年 3月 22日
应用手册 使用 SN74LVC1G123 单稳多谐振荡器进行设计 (Rev. A) PDF | HTML 下载英文版本 (Rev.A) PDF | HTML 2021年 7月 20日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日

设计和开发

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评估板

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
下载英文版本 (Rev.B): PDF | HTML
TI.com 上无现货
评估板

14-24-NL-LOGIC-EVM — 通用 14 至 24 引脚无铅封装评估模块

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
用户指南: PDF | HTML
下载英文版本 (Rev.A): PDF | HTML
TI.com 上无现货
仿真模型

HSPICE Model for SN74LV123A

SCLJ019.ZIP (111 KB) - HSpice Model
下载
仿真模型

SN74LV123A IBIS Model (Rev. A)

SCEM125A.ZIP (21 KB) - IBIS Model
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仿真模型

SN74LV123A PSpice Model (Rev. C)

SCEM569C.ZIP (384 KB) - PSpice Model
下载
封装 引脚数 下载
SOIC (D) 16 了解详情
SOP (NS) 16 了解详情
SSOP (DB) 16 了解详情
TSSOP (PW) 16 了解详情
TVSOP (DGV) 16 了解详情
VQFN (RGY) 16 了解详情
应遵守 TI 的评估模块标准条款与条件.

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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