SN74HC139-Q1
- Qualified for Automotive Applications
- Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive up to Ten LSTTL Loads
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 10 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
- ESD Protection Level per AEC-Q100 Classification
- 2000-V (H2) Human-Body Model
- 200-V (M3) Machine Model
- 1000-V (C5) Charged-Device Model
The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Dual 2-Line to 4-Line Decoder/Demultiplexer 数据表 (Rev. B) | 2008-4-24 | |||
| 应用简报 | TI 逻辑系列的内插规格值 | PDF | HTML | PDF | HTML | 2026-4-17 | ||
| 更多文献资料 | 汽车逻辑器件 | 英语版 | 2014-2-5 |
设计与开发
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |