产品详情

Technology family LV-A Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 12 IOH (max) (mA) -12 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 12 IOH (max) (mA) -12 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Live insertion, Partial Power Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Live insertion, Partial Power Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

The SNx4LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V VCC operation.

The SNx4LV02A devices perform the Boolean function Y = A + B or Y = AB in positive logic.

The SNx4LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V VCC operation.

The SNx4LV02A devices perform the Boolean function Y = A + B or Y = AB in positive logic.

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类型 标题 下载最新的英语版本 日期
* 数据表 SNx4LV02A Quadruple 2-Input Positive-NOR Gates 数据表 (Rev. K) PDF | HTML 2015年 2月 18日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
评估板

14-24-NL-LOGIC-EVM — 采用 14 引脚至 24 引脚无引线封装的逻辑产品通用评估模块

14-24-EVM 是一款灵活的评估模块 (EVM),旨在支持具有 14 引脚至 24 引脚 BQA、BQB、RGY、RSV、RJW 或 RHL 封装的任何逻辑或转换器件。

用户指南: PDF | HTML
英语版 (Rev.A): PDF | HTML
TI.com 上无现货
仿真模型

SN74LV02A Behavioral SPICE Model

SCLM192.ZIP (7 KB) - PSpice Model
仿真模型

SN74LV02A IBIS Model

SCEM120.ZIP (16 KB) - IBIS Model
封装 引脚 下载
SOIC (D) 14 查看选项
SOP (NS) 14 查看选项
SSOP (DB) 14 查看选项
TSSOP (PW) 14 查看选项
TVSOP (DGV) 14 查看选项
VQFN (RGY) 14 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

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