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SN74CBT3125C

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具有 –2V 下冲保护的 5V、1:1 (SPST)、4 通道 FET 总线开关

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SN74CBT3125C

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产品详情

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 3 CON (typ) (pF) 12.5 ON-state leakage current (max) (µA) 10 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 3 CON (typ) (pF) 12.5 ON-state leakage current (max) (µA) 10 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog
SOIC (D) 14 51.9 mm² 8.65 x 6 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 SSOP (DBQ) 16 29.4 mm² 4.9 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low On-State Resistance (ron) Characteristics
          (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
         (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption
         (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low On-State Resistance (ron) Characteristics
          (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
         (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption
         (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating

The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3125C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE\, 2OE\, 3OE\, 4OE\) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE\ is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3125C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE\, 2OE\, 3OE\, 4OE\) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE\ is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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类型 项目标题 下载最新的英语版本 日期
* 数据表 SN74CBT3125C 数据表 (Rev. A) 2003年 10月 15日
更多文献资料 选择正确的德州仪器 (TI) 信号开关 (Rev. E) PDF | HTML 下载英文版本 (Rev.E) PDF | HTML 2022年 8月 5日
更多文献资料 CBT-C、CB3T 和 CB3Q 信号开关系列 (Rev. C) PDF | HTML 下载英文版本 (Rev.C) PDF | HTML 2022年 3月 11日
更多文献资料 多路复用器和信号开关词汇表 (Rev. B) 下载英文版本 (Rev.B) PDF | HTML 2022年 3月 11日
更多文献资料 利用关断保护信号开关消除电源时序 (Rev. C) 下载英文版本 (Rev.C) PDF | HTML 2021年 10月 21日
选择指南 Little Logic Guide 2014 (Rev. G) 2018年 7月 6日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
更多文献资料 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日
选择指南 小尺寸逻辑器件指南 (Rev. E) 下载最新的英文版本 (Rev.G) 2012年 7月 16日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
更多文献资料 Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
更多文献资料 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
更多文献资料 Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日

设计和开发

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用户指南: PDF
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仿真模型

SN74CBT3125C HSPICE Model (Rev. A)

SCDJ018A.ZIP (62 KB) - HSpice Model
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仿真模型

SN74CBT3125C IBIS Model

SCDM046.ZIP (27 KB) - IBIS Model
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封装 引脚数 下载
SOIC (D) 14 了解详情
SSOP (DB) 14 了解详情
SSOP (DBQ) 16 了解详情
TSSOP (PW) 14 了解详情
VQFN (RGY) 14 了解详情

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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