SN74AVC1T45

Name: SN74AVC1T45
Brand: TI
SKU: SN74AVC1T45
Price: 0.18 USD

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具有可配置电压转换和三态输出的单位双电源总线收发器

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数据表

document-pdfAcrobat SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 数据表 (Rev. H) (英文) PDF | HTML

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SN74AXC1T45

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单位双电源总线收发器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC1T45

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数据表

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产品详情

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (MBps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (MBps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

6

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

6

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

6

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

6

3 mm² 2 x 1.5

Available in the Texas Instruments NanoFree Package
Fully Configurable Dual-Rail Design Allows Each Port to
Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
V_CC Isolation Feature - If Either V_CC
Input Is At GND, Both Ports Are In The High-Impedance State
DIR Input Circuit Referenced to V_CCA
±12-mA Output Drive at 3.3 V
I/Os Are 4.6-V Tolerant
I_off Supports Partial-Power-Down Mode Operation
Typical Max Data Rates
- 500 Mbps (1.8-V to 3.3-V Translation)
- 320 Mbps (<1.8-V to 3.3-V Translation)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- ±2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- ±1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Fully Configurable Dual-Rail Design Allows Each Port to
Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
V_CC Isolation Feature - If Either V_CC
Input Is At GND, Both Ports Are In The High-Impedance State
DIR Input Circuit Referenced to V_CCA
±12-mA Output Drive at 3.3 V
I/Os Are 4.6-V Tolerant
I_off Supports Partial-Power-Down Mode Operation
Typical Max Data Rates
- 500 Mbps (1.8-V to 3.3-V Translation)
- 320 Mbps (<1.8-V to 3.3-V Translation)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- ±2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- ±1000-V Charged-Device Model (C101)

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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	类型	项目标题		下载最新的英语版本	日期
*	数据表	SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 数据表 (Rev. H)	PDF \| HTML		2014年 12月 23日
	EVM 用户指南	AVCLVCDIRCNTRL-EVM 评估模块 (Rev. B)	PDF \| HTML	下载英文版本 (Rev.B)	2021年 8月 17日
	选择指南	Voltage Translation Buying Guide (Rev. A)			2021年 4月 15日
	选择指南	Logic Guide (Rev. AB)			2017年 6月 12日
	应用手册	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)			2015年 12月 2日
	应用手册	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)			2015年 4月 30日
	选择指南	逻辑器件指南 2014 (Rev. AA)		下载最新的英文版本 (Rev.AB)	2014年 11月 17日
	测试报告	TI Power Reference Design for Xilinx® Artix®-7 (AC701)			2014年 5月 12日
	用户指南	PMP7977 User's Guide			2013年 9月 11日
	用户指南	LOGIC Pocket Data Book (Rev. B)			2007年 1月 16日
	应用手册	选择正确的电平转换解决方案 (Rev. A)		下载英文版本 (Rev.A)	2006年 3月 23日
	应用手册	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection			2004年 7月 8日
	更多文献资料	LCD Module Interface Application Clip			2003年 5月 9日
	用户指南	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)			2002年 8月 20日
	更多文献资料	Standard Linear & Logic for PCs, Servers & Motherboards			2002年 6月 13日
	应用手册	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)			2002年 5月 22日
	应用手册	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)			1999年 7月 7日
	应用手册	AVC Logic Family Technology and Applications (Rev. A)			1998年 8月 26日

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