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可编程和可变增益放大器（PGA 和 VGA）

PGA116

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具有 10 通道多路复用器的零漂移、100µV 偏移电压、12nV/√Hz 噪声、RRO（二进制增益）可编程增益放大器

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数据表

PGA116

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数据表 立即订购

产品详情

PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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功能与比较器件相同且具有相同引脚。
PGA117 正在供货 具有 10 通道多路复用器的零温漂、100µV 失调电压、12nV/√Hz 噪声、RRO（范围增益）可编程增益放大器 This device offers scope gains 1, 2, 5, 10, 20, 50, 100, 200 instead of binary gains
功能与比较器件相同但引脚有所不同。
PGA113 正在供货 具有 2 通道多路复用器的零温漂、100µV 失调电压、12nV/√Hz 噪声、RRO（范围增益）可编程增益放大器 This device offers 2 channel mux instead of 10 channel mux, and scope gains instead of binary gains.
PGA112 正在供货 具有 2 通道多路复用器的零温漂、100µV 失调电压、12nV/√Hz 噪声、RRO（二进制增益）可编程增益放大器 This device offers 2 channel mux instead of 10 channel mux.

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* 数据表 PGA11x Zerø-Drift Programmable Gain Amplifier With Mux 数据表 (Rev. C) PDF | HTML 2015-11-30

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

参考设计

TIDA-00191 — 具有增强电流范围的电机电子过载继电器模拟前端

该参考设计是电子过载继电器的模拟前端 (AFE)，用于监测和保护电机免受过流或欠流事件影响。对于开发人员而言，这是为工业应用中敏感交流电机设计过载继电器的理想工具。这款基于可编程增益放大器 (PGA) 的模拟前端旨在作为一个简单的评估平台，实现精确的且业界领先的 10:1 满负载安培 (FLA) 范围，并在 –10 至 +70°C 的温度范围内具有可重复性。

支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (PW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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