产品详细信息

Function Clock generator Number of outputs 2 Output frequency (Max) (MHz) 148.5 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) 0 to 70 Features Multi-rate video clock generator with Genlock Rating Catalog
Function Clock generator Number of outputs 2 Output frequency (Max) (MHz) 148.5 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) 0 to 70 Features Multi-rate video clock generator with Genlock Rating Catalog
WQFN (RTV) 32 25 mm² 5 x 5
  • Two Simultaneous LVDS Output Clocks with
    Selectable Frequencies and Hi-Z Capability:
    • SD Clock: 27 MHz or 67.5 MHz
    • HD Clock: 74.25 MHz, 74.25/1.001 MHz,
      148.5 MHz or 148.5/1.001 MHz
  • Low-Jitter Output Clocks May Be Directly
    Connected to an FPGA Serializer to Meet SMPTE
    SDI Jitter Specifications
  • Top of Frame (TOF) Pulse with Programmable
    Output Format Timing and Hi-Z Capability
  • Two reference ports (A and B) With H and V Sync
    Inputs
  • Supports Cross-Locking of Input and Output
    Timing
  • External Loop Filter Allows Control of Loop
    Bandwidth, Jitter Transfer, and Lock Time
    Characteristics
  • Free Run or Holdover Operation on Loss of
    Reference
  • User-Defined Free Run Control Voltage Input
  • I2C Interface and Control Registers
  • 3.3-V and 2.5-V Supplies
  • Two Simultaneous LVDS Output Clocks with
    Selectable Frequencies and Hi-Z Capability:
    • SD Clock: 27 MHz or 67.5 MHz
    • HD Clock: 74.25 MHz, 74.25/1.001 MHz,
      148.5 MHz or 148.5/1.001 MHz
  • Low-Jitter Output Clocks May Be Directly
    Connected to an FPGA Serializer to Meet SMPTE
    SDI Jitter Specifications
  • Top of Frame (TOF) Pulse with Programmable
    Output Format Timing and Hi-Z Capability
  • Two reference ports (A and B) With H and V Sync
    Inputs
  • Supports Cross-Locking of Input and Output
    Timing
  • External Loop Filter Allows Control of Loop
    Bandwidth, Jitter Transfer, and Lock Time
    Characteristics
  • Free Run or Holdover Operation on Loss of
    Reference
  • User-Defined Free Run Control Voltage Input
  • I2C Interface and Control Registers
  • 3.3-V and 2.5-V Supplies

The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).

The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).

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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 LMH1982 Multi-Rate Video Clock Generator With Genlock 数据表 (Rev. D) 2015年 9月 30日
选择指南 Broadcast and Professional Video Interface Solutions (Rev. E) 2017年 4月 5日
技术文章 How to select an optimal clocking solution for your FPGA-based design 2015年 12月 9日
技术文章 Clocking sampled systems to minimize jitter 2014年 7月 31日
技术文章 Timing is Everything: How to optimize clock distribution in PCIe applications 2014年 3月 28日
用户指南 AN-1841 LMH1982 Evaluation Board User Guide (Rev. A) 2013年 4月 26日
应用手册 Demonst SMPTE-Compliant SDI Out Jittr Using LMH1982 & Virtx-5 GTP Xmittr (Rev. A) 2013年 4月 26日
应用手册 Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 2013年 4月 26日
更多文献资料 LMH1982 SD/HD Video Clock and Timing Generator with Genlock Capability 2012年 1月 25日
应用手册 Application Note 1841 LMH1982 Evaluation Board User Guide (cn) 下载最新的英文版本 (Rev.A) 2008年 5月 21日
设计指南 Broadcast Video Owner's Manual 2006年 11月 17日

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LMH1982SQEEVAL — 具有 LMH1981 HD/SD 视频同步分离器的 LMH1982 多速率视频时钟发生器 EVM

The LMH1982 evaluation board platform was designed by National Semiconductor to demonstrate the excellent clock jitter performance of the LMH1982 multi-rate video clock and timing generator in a genlock application with the LMH1981 multi-format video sync separator. The evaluation platform consists (...)

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LMH1982APP-SW — LMH1982 软件设置 - 具有同步锁相的多速率视频时钟发生器

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