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LMH0341

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具有环路输出和 LVDS 接口的 3G HD/SD DVB-ASI SDI 解串器

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LMH0341

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产品详情

Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 520 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 520 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² 7 x 7
  • 5-Bit LVDS Interface
  • No External VCO or Clock Required
  • Reclocked Serial Loopthrough With Cable Driver
  • Powerdown Mode
  • 3.3V SMBus Configuration Interface
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to +85°C

Key Specifications

  • Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
  • Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
  • 0.6 UI Minimum Input Jitter Tolerance

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

  • 5-Bit LVDS Interface
  • No External VCO or Clock Required
  • Reclocked Serial Loopthrough With Cable Driver
  • Powerdown Mode
  • 3.3V SMBus Configuration Interface
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to +85°C

Key Specifications

  • Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
  • Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
  • 0.6 UI Minimum Input Jitter Tolerance

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.

The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.

The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.

The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.

The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.

The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F 数据表 (Rev. Q) 2013年 4月 16日
选择指南 Broadcast and Professional Video Interface Solutions (Rev. E) 2017年 4月 5日
应用手册 AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 2013年 4月 26日
应用手册 AN-1972 Board Layout Challenges in Serial Digital Interface (Rev. C) 2013年 4月 26日
应用手册 AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) 2013年 4月 26日
应用手册 AN-2145 Power Considerations for SDI Products (Rev. B) 2013年 4月 26日
应用手册 AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013年 4月 26日
应用手册 Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 2013年 4月 26日
应用手册 High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 2009年 11月 12日
应用手册 Application Note 1972 Board Layout Challenges in Serial Digital Interface (cn) 2009年 9月 13日
应用手册 DS25CP104 in 3G SDI Router Application 2008年 8月 20日
应用手册 A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video 2008年 3月 18日
设计指南 Broadcast Video Owner's Manual 2006年 11月 17日

设计和开发

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代码示例或演示

BROADCAST_VIDEO_SERDES_IP — 用于 LVDS 接口 SDI 串行器/解串器的广播视频支持代码

We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
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用户指南: PDF
英语版 (Rev.A): PDF
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封装 引脚 CAD 符号、封装和 3D 模型
WQFN (RHS) 48 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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