LM5025
- Internal Start-Up Bias Regulator
- 3-A Compound Main Gate Driver
- Programmable Line Undervoltage Lockout (UVLO)
With Adjustable Hysteresis - Voltage Mode Control With Feed-Forward
- Adjustable Dual-Mode Overcurrent Protection
- Programmable Overlap or Deadtime Between the
Main and Active Clamp Outputs - Volt × Second Clamp
- Programmable Soft-Start
- Leading Edge Blanking
- Single Resistor Programmable Oscillator
- Oscillator UP and DOWN Sync Capability
- Precision 5-V Reference
- Thermal Shutdown
The LM5025 PWM controller contains all of the features necessary to implement power converters using the active clamp and reset technique. The device can be configured to control either a P-channel clamp switch or an N-channel clamp switch. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp and reset techniques.
Two control outputs are provided, the main power switch control (OUT_A), and the active clamp switch control (OUT_B). The active clamp output can be configured for either a specified overlap time (for P-channel switch applications) or a specified deadtime (for N_channel applications). The two internal compound gate drivers parallel both MOS and bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1 MHz and total PWM and current sense propagation delays less than 100 ns.
The LM5025 includes a high-voltage start-up regulator that operates over a wide input range of 13 V to 90 V. Additional features include: line undervoltage lockout (UVLO), soft-start, oscillator UP and DOWN sync capability, precision reference and thermal shutdown.
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封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
TSSOP (PW) | 16 | Ultra Librarian |
WSON (NHQ) | 16 | Ultra Librarian |
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