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参数

Function Serializer Color depth (bpp) 18 Pixel clock min (MHz) 5 Pixel clock (Max) (MHz) 43 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Capable to Drive up to 10 meters STP Cable, Hot Plug Support Signal conditioning Pre-Emphasis, VOD Select EMI reduction LVDS, Slew Rate Control, Progressive Turn On (PTO), BIST Diagnostics BIST Total throughput (Mbps) 1032 Rating Catalog Operating temperature range (C) -40 to 105 open-in-new 查找其它 显示 SerDes

封装|引脚|尺寸

TQFP (PFB) 48 81 mm² 9 x 9 open-in-new 查找其它 显示 SerDes

特性

  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
    Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
    AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
    ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
    Spectrum Input; Data Randomization and
    Shuffling on Serial Link; Deserializer Provides
    Adjustable PTO (Progressive Turnon) LVCMOS
    Outputs
  • @Speed BIST (Built-In Self-Test) to Validate
    LVDS Transmission Path
  • Individual Power-Down Controls for Both
    Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
    TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
    DS90C241/DS90C124
open-in-new 查找其它 显示 SerDes

描述

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

open-in-new 查找其它 显示 SerDes
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open-in-new 产品比较
与相比较的设备类似但功能不等效:
DS90UR241-Q1 正在供货 5-43MHz DC 平衡 24 位 FPD 链接 II 串行器 Automotive grade version

技术文档

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

评估板 下载
document-generic 用户指南
$249.00
说明

The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.

The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. The (...)

设计工具和仿真

仿真模型 下载
SNLM026.ZIP (7 KB) - IBIS Model
仿真工具 下载
document-generic 用户指南 document-generic 下载英文版本 (Rev.A)
CAD/CAE 符号 下载
SNLC003.ZIP (125 KB)

CAD/CAE 符号

封装 引脚 下载
TQFP (PFB) 48 视图选项

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