DS90UH928Q-Q1
- Qualified for Automotive Applications AEC-Q100
- Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level ±8 kV
- Device CDM ESD Classification Level C6
- Integrated HDCP Cipher Engine with On-Chip Key Storage
- Supports HDCP Repeater Application
- Bidirectional Control Channel Interface with I2C Compatible Serial Control Bus
- Low EMI FPD-Link Video Output
- Supports High Definition (720p) Digital Video
- RGB888 + VS, HS, DE and I2S Audio Supported
- 5 MHz to 85 MHz Pixel Clock Support
- Up to 4 I2S Digital Audio Outputs for Surround Sound Applications
- 4 Bidirectional GPIO Channels with 2 Dedicated Pins
- Single 3.3 V supply with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
- AC-Coupled STP Interconnect Up to 10 Meters
- DC-Balanced and Scrambled Data with Embedded Clock
- Adaptive Cable Equalization
- Image Enhancement (White Balance & Dithering) and Internal Pattern Generation
- Backward Compatible Modes
The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90UH928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP 数据表 (Rev. C) | PDF | HTML | 2016-5-16 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DS90UB928QEVM — DS90UB928QEVM FPD-Link III 解串器评估模块
DS90UH928QEVM — DS90UH928QEVM FPD-Link III 解串器评估模块
德州仪器 (TI) 的 DS90UH928QEVM 评估模块 (EVM) 可帮助系统设计人员评估 DS90UH928Q 5MHz-85MHz FPD-Link III 解串器 (DES) 的操作和性能。该器件将通过单一屏蔽双绞线 (STP) 传输的高速串行 FPD-Link III 接口转换为四个与 FPD-Link 兼容的 LVDS 数据输出对和一个 LVDS 时钟。
DS90UH928QEVM 板有一个用于连接到 FPD-Link 输出的 20 个位置的 IDC 连接器，和一个用于将汽车级 STP 电缆连接到 FPD-Link III 输入的 HSD 车用连接器。所包含的 SMA (...)
ALP — Analog LaunchPad Framework Utility
ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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