DS90LV110AT
- Low jitter 400 Mbps fully differential data path
- 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 400 Mbps
- Single +3.3 V Supply
- Balanced output impedance
- Output channel-to-channel skew is 35ps (typ)
- Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
- LVDS receiver inputs accept LVPECL signals
- LVDS input failsafe
- Fast propagation delay of 2.8 ns (typ)
- Receiver open, shorted, and terminated input failsafe
- 28 lead TSSOP package
- Conforms to ANSI/TIA/EIA-644 LVDS standard
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DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz.
The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the enable pin.
For more details, please refer to the APPLICATION INFORMATION section of this datasheet.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe 数据表 (Rev. J) | 2013-4-13 | |||
| 应用手册 | An Overview of LVDS Technology | 1998-10-5 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TSSOP (PW) | 28 | Ultra Librarian |
订购和质量
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